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In the news

A Deep Dive into AI Chip Arithmetic Engines

By Sergio Marchese, Technical Marketing, OneSpin

Artificial intelligence (AI) is steadily progressing toward advanced, high-value applications that will have a profound impact on our society. Automobiles that can drive themselves are perhaps the most talked about, imminent technological revolution, but there are many more applications of AI.

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OneSpin, Trinamic, MINRES, and GreenWaves Introduce the RISC-V EMEA Roadshow

As RISC-V’s community grows ever larger, the RISC-V Foundation has announced its 2019 EMEA roadshow, Getting Started with RISC-V.

Electronics Point talked to three experts who will be speaking at the event: OneSpin’s Rob van Blommestein, Trinamic’s Onno Martens, MINRES Technologies’ Eyck Jentzsch, and GreenWaves Technologies’ Martin Croome.

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Automated connectivity checking with formal verification

By Tom Anderson, Technical Marketing, OneSpin

Formal verification traditionally has been regarded as an advanced technique for experts to thoroughly verify indi- vidual blocks of logic, or perhaps small clusters of blocks. The appeal of formal techniques is the exhaustive analysis of all possible behavior for the design being verified. This stands in sharp contrast to simulation, which exercises only a tiny fraction of possible behavior by running specific tests. If no test triggers a design bug, the bug will not be found. If the bug is triggered but no change in results is observed, the bug will not be found. Given a sufficiently robust set of properties to describe intended behavior, formal tools can not only find all bugs but also prove that there are no more bugs to be found.

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FPGA Design Tradeoffs Getting Tougher

By Ann Steffora Mutschler, Semiconductor Engineering | Feat. Sasa Stamenkovic, senior field applications engineer, OneSpin Solutions


In the past, FPGAs were considered a relatively quick and simple way to get to market before committing to the cost and time of developing an ASIC. But today, both FPGAs and eFPGAs are being used in the most demanding applications, including cloud computing, AI, machine learning, and deep learning. In some cases, they are being combined with an ASIC or some other type of application-specific processor or accelerator inside a chip, a package or a system. As a result, requirements for effective power, performance, and area (PPA) are every bit as strict as for ASICs and full-custom chips, and the tradeoffs are equally complicated and often intertwined.

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IP’s Growing Impact On Yield And Reliability

By Ann Steffora Mutschler, Semiconductor Engineering | Featuring Vladislav Palfy, Director of Applications Engineering, OneSpin

Managing IP quality and compatibility is becoming more difficult at advanced nodes and in safety-critical markets.

Chipmakers are finding it increasingly difficult to achieve first-pass silicon with design IP sourced internally and from different IP providers, and especially with configurable IP.

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Fachartikel von Jörg Grosse, Sergio Marchese, OneSpin Solutions

Die Sicherheit von applikationsspezifischen Automotive-Chips beurteilen

ASICs, FPGAs und SoCs unterliegen dem Risiko, dass während des Betriebs Fehler auftreten. Dabei ist FMEDA entscheidend für die Analyse des Ausfallrisikos. Ist dabei eine Automatisierung möglich?

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Chip Security Needs A New Language

By Sven Beyer and Sergio Marchese, OneSpin Solutions

SystemVerilog assertions can nicely capture many hardware requirements. However, more is needed for security verification.

Safety- and security-critical systems, such as connected autonomous vehicles, require high-integrity integrated circuits (ICs). Functional correctness and safety are necessary to establish IC integrity, but not sufficient. Security is another critical pillar of IC integrity. Systems and products using ICs with security vulnerabilities ultimately undermine the safety and privacy of people. However, hardware security is still in its infancy.

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Automated Connectivity Test - QED [German]

By Tom Anderson, Technical Marketing Consultant, OneSpin Solutions


Automatisierte Konnektivitatsprufung. Die Verbindungen zwischen den Designblocken und I/O-Zellen komplexer Chips lassen sich nicht mittels Inspektion verifizieren. Simulation und Emulation konnen zwar Bugs aufspuren, bleiben aber unvolistandig. Formale Tools dagegen finden nicht nur alle Fehler – sie konnen das auch beweisen.

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