close By using this website, you agree to the use of cookies. Detailed information on the use of cookies on this website can be obtained on OneSpin's Privacy Policy. At this point you may also object to the use of cookies and adjust the browser settings accordingly.

In the news

Week In Review: Design, Low Power

By Jesse Allen, Semiconductor Engineering

OneSpin Solutions unveiled a formal RISC-V Verification App. The App is intended to exhaustively verify that RSIC-V cores are developed and integrated with zero bug escapes and guarantee full compliance with the ISA, even with the range of configuration options available. OneSpin says the automated solution needs only a few days to set up and only two hours to run on a complete core. In addition, OneSpin’s 360 EC-FPGA now supports three Intel FPGA families, Stratix 10, Arria 10, and Cyclone V using Intel Quartus software for synthesis and place-and-route. The company says the move to support FPGAs used in high-bandwidth applications meets demand from verification engineers for formal equivalence checking solutions that ensure functional correctness of FPGA designs. The tool is implemented in the FPGA flow from RTL to place-and-route to check RTL code against a post-synthesis, gate-level netlist.

Read more

OneSpin Adds SEC for Intel FPGAs and App for RISC-V ISA Compliance

By TDF Editorial Staff, Tech Design Forum

OneSpin Solutions has extended its EC-FPGA automated sequential equivalence checking software to cover three of Intel’s field programmable gate array (FPGA) lines: Stratix 10, Arria 10 and Cyclone V.

The company has also launched an app for use inside its RISC-V Integrity Verification Solution aimed at safety- and security-critical applications and specifically targeting the increasingly popular open-source core.

Read more

Evolution of Verification Engineers (Experts at the Table, Part 3)

By Brian Bailey, Semiconductor Engineering | Feat. Tom Anderson, Technical Marketing Consultant, and Jim Hogan, Board Director, OneSpin

The role of a verification engineer will change and start to look a lot like knowledge management.

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief executive office for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions architect for Cadence Design Systems; and Tom Anderson, technical marketing consultant for OneSpin Solutions. What follows are excerpts of that conversation.

[...]

Anderson: We are dancing around the idea of correct by construction. It has been around forever. Would you want a model that you don’t have to verify? That is the goal of correct by construction. You have a model that is correct, maybe through exploration, maybe through other techniques that you used to validate and verify what you are worried about. But it is a single model, and from that you generate the design. Maybe we are getting to the point where the top level of an SoC, defined to be correct by construction, may actually work.

Read more

Incremental System Verification (Experts at the Table, Part 2)

By Brian Bailey, Semiconductor Engineering | Feat. Tom Anderson, Technical Marketing Consultant, OneSpin; and Jim Hogan, Board Director, OneSpin

How does a PSS model get verified and who will create that model? What happens when models extend beyond the specification?

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief executive office for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions architect for Cadence Design Systems; and Tom Anderson, technical marketing consultant for OneSpin Solutions. What follows are excerpts of that conversation.

[...]

Anderson: This is certainly an example of the way in which verification will influence design. You are playing with a level of parameters that affect what the hardware does. This is another dimension of the general problem.

Read more

Chiplet Momentum Builds, Despite Tradeoffs

By Brian Bailey, Semiconductor Engineering | Feat. Sven Beyer, Product Manager Design Verification, OneSpin

Pre-characterized tiles can move Moore’s Law forward, but it’s not as easy as it looks.

Chip design is a series of tradeoffs. Some are technical, others are related to cost, competitive features or legal restrictions. But with the nascent ‘chiplet’ market, many of the established balance points are significantly altered, depending on market segments and ecosystem readiness.

[...]

"The chiplet also offers more opportunities for both security vulnerabilities and hidden hardware Trojans," cautions Sven Beyer, product manager for design verification at OneSpin Solutions. "Integrators will expect the vendor to verify these aspects of integrity. The SoC team may wish to re-run some aspects of standalone IP verification as part of screening vendors and evaluating chiplets."

Read more

Formal Engines Learn from Experience

By Chris Edwards, Tech Design Forum | Feat. Dominik Strasser, VP Engineering, OneSpin

[...]

OneSpin’s work found that solver orchestration based on machine learning is effective. The company is armed with more than two decades worth of collected designs that extend as far back as the team’s original work at Siemens in the early 1990s.

Dominik Strasser, vice president of engineering at OneSpin, says with the machine-learning functions: “Users do not normally have to pick proof algorithms and we now have a system that has faster proofs for time-to-hold,” adding that time-to-fail has rarely been an issue.

[...]

As part of its ongoing work into applying AI to formal, a new project at OneSpin is aimed at helping with the debug process. “The tool finds out which part is the culprit. This is a very difficult problem to solve and a task for the future but we have some intermediate results. But don’t hold your breath,” Strasser says.

Another path OneSpin aims to pursue is using deep learning to analyse verification data. “Maybe then the runtime prediction will get better results,” Strasser hopes.

Read more

ESD Alliance Elects 10-Member Governing Council

Three New Members Join Returning Members

The Electronic System Design (ESD) Alliance, a SEMI Strategic Association Partner, today welcomed its newly elected 10-member Governing Council who will serve a two-year term.

Returning Governing Council members are:

Dr. Aart de Geus, chairman and co-chief executive officer (co-CEO) of Synopsys, Inc.

Dean Drako, president and CEO at IC Manage

Dr. John Kibarian, president and CEO of PDF Solutions, Inc.

Dr. Walden C. Rhines, CEO Emeritus of Mentor, a Siemens business

Simon Segars, CEO at Arm

Lip-Bu Tan, CEO of Cadence Design Systems

New Governing Council members are Dr. Raik Brinkmann, president and CEO of OneSpin Solutions, Dr. Prakash Narain, president and CEO of Real Intent and David Dutton, CEO of Silvaco. Robert P. Smith, executive director of the ESD Alliance, is also a member of the council.

The Governing Council was elected by the ESD Alliance’s voting members during the voting period that ended May 3. The new chair will be elected at the first meeting of the Governing Council meeting Thursday, May 23.

Read more

Verification Challenges for RISC-V Adoption

By Tom Anderson, Technical Marketing Consultant, OneSpin Solutions | Posted on GSA Forum

Just a few years ago, the idea of an open-specification processor architecture with open-source implementations available would have been dismissed by many. Modern processor designs are highly complex, with such advanced features as multi-stage pipelines, multi-level caches, out-of-order execution, branch prediction, and memory pre-fetching. Beyond the hardware design, a huge ecosystem is needed. Reference design kits and software development platforms are essential. Operating systems and applications must be ported to the new architecture. A significant portion of the system-on-chip (SoC) industry must design-in the new processor and validate it in silicon. These challenges have appeared daunting indeed.

However, the introduction of the RISC-V architecture has defied conventional wisdom and is starting to disrupt the processor world. The original design was developed in the EECS Department at the University of California, Berkeley. The instruction set architecture (ISA), the primary processor specification, is now supported by the RISC-V Foundation. Its more than 200 members span semiconductors, systems, intellectual property (IP), software, academia, and more. Clearly there is a great deal of interest in this topic, but the industry has moved well beyond just curiosity. Many RISC-V cores, and even some SoCs built around these cores, are available as open source. Commercial cores also exist, and chips containing RISC-V processors are shipping. Many software titles have already been ported.

Read more

Press Contact

portrait of Nanette Collins

Nanette Collins
» nanette@nvc.com
» +1 617 437 1822