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In the news

An Effective Way to Verify RISC-V Cores (Swedish)

By Nicolae Tusinshci and Wei Wei Chen, OneSpin: A Siemens Business

Modern processor designs present us with some of the toughest challenges in hardware verification. This is especially true when it comes to RISC-V processor cores, where there are a number of variations and implementations from a myriad of different sources. The article by W. W. Chen, N. Tusinschi and T. L. Anderson, OneSpin Solutions, was presented at DVCon Europe 2020 and describes a verification methodology available to both RISC-V kernel vendors and SOC teams working to integrate these kernels. It deals with functional correctness including compliance, detection of security vulnerabilities and verification of the reliability that no malicious logic has been entered. Detailed examples of design bugs discovered in real RISC-V cores have been included.

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Technologist Interview: What Siemens’ Acquisition of OneSpin Means for Formal Verification – and You

by Tom Fitzpatrick, Harry Foster and Dominik Strasser, Siemens EDA

in May 2021 Siemens EDA acquired OneSpin Solutions, combining Siemens' Questa Formal products and expertise (with roots and team members from 0-In) with OneSpin’s “apps first” approach to key growth markets including Trust&Security, Safety, RISC-V, and FPGAs. The combination adds to a cohesive Siemens EDA verification solution spanning simulation, formal, emulation, and prototyping. To find out what this means for the future of formal technology – and how end-users will benefit -- I’ve interviewed Formal experts Harry Foster (of the Wilson Survey fame, DAC 2021 General Chair chairman, among other roles), and Dominik Strasser (a co-founder of OneSpin; now in Siemens R&D).

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Always On, Always At Risk

By Ed Sperling, Semiconductor Engineering

Chip security concerns rise with more processing elements, automatic wake-up, over-the-air updates, and greater connectivity.

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A Core Challenge

By Nicolae Tusinschi, OneSpin a Siemens Business

A common verification methodology available to both RISC-V core providers and SoC teams integrating these cores is required.

Modern processor designs present some of the toughest hardware verification challenges. Verification is particularly challenging for RISC-V processor core designs, with many providers and many variations of implementation.

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