close By using this website, you agree to the use of cookies. Detailed information on the use of cookies on this website can be obtained on OneSpin's Privacy Policy. At this point you may also object to the use of cookies and adjust the browser settings accordingly.

Certified IC Integrity Solutions to Develop Functionally Correct, Safe, Secure, and Trusted Integrated Circuits

OneSpin provides the most advanced and robust verification platform to address today's critical IC integrity issues. Our experts are dedicated to solving the toughest next-generation verification challenges and providing solutions that enable design teams to create SoCs that are functionally correct, safe, secure, and trusted.

IC Integrity Solutions

Vertical Market Solutions

OneSpin Customer Case Studies


OneSpin is proud to partner with leaders worldwide in automotive, industrial, defense, avionics, artificial intelligence, consumer electronics, and communications.


Our Customer Stories page provides a comprehensive look at how these companies are using our advanced verification solutions and the results that were achieved.


Stories are categorized by product type and industry application.

Watch our latest videos

In The News

Press Releases


The CV32E40P core, is the first open-source core for high-volume chips verified with the state-of-the-art process required for high-integrity, commercial SoCs. OneSpin is a key contributor. The OneSpin RISC-V integrity formal verification solution has systematically detected corner-case bugs in the exception logic and pipeline. These issues would only be triggered under rare conditions in the instruction sequence, memory stalls, and Control and Status Register programming. Constrained-random simulation tests to find these issues would require large investments in development and simulation time.

Steve Richmond, Verification Manager, Silicon Labs

The pinpointing of the issues' root cause was impressive and a massive time-saver in debug time. The solution also showed almost zero noise in detecting real RTL bugs, as opposed to other approaches where the issues reported often lead to fixes in the verification environment.

Arjan Bink, Principal Architect, Silicon Labs

The complete, formal-based processor verification approach ... uses Operational SVA to formalize the RISC-V ISA and proves that the resulting set of assertions is free from gaps and inconsistencies. This notion of completeness is precise, highly rigorous, and mathematically provable ... Unlike advanced simulation test benches or alternative formal verification approaches, the complete set of properties detects many types of RTL-based, arbitrarily complex hardware Trojans.

Paul McHale, Principal Engineer, EDAPTIVE COMPUTING

"The Connectivity XL approach has been successfully applied to a multi-billion-gate, 7nm Xilinx SoC, delivering conclusive proofs for over one million complex connections, most of them including thousands of signals in the connectivity path, delays, and multiplexing conditions. The approach has detected multiple bugs that would have been much harder, or even impossible, to detect with other formal or simulation techniques."

Imtiyaz Ron, Xilinx, senior engineering manager, design verifcation, Xilinx

"The combined engineering effort to set up the extraction of the decoder subparts using the FCA app, and the fault classification using the FDA app was 3 days. ... The overall runtime for the fault classification task for all scenarios reported is under 1 hour."

Jörg Koch, senior manager, Renesas

"Onespin ... supports shared responsibility between design and verification, efficient apps to perform debug and verification, [and] interoperability with the 3rd party Verification Management tools."

Antti Rautakoura, SoC/ASIC verification specialist, Nokia

"GapFree ensures highest verification quality ... very good improvement in verification productivity"

Keerthi Devarajegowda, verification expert, Infineon Technologies

"Easy and straightforward setup [of EC-FPGA] based on simple template script provided by OneSpin support ... Designs [were] proven to be equivalent after total run time of less than one hour."

Jürgen Dennerlein, product development, IC hardware development expert, and platform architect, Framatome

“We’re delighted to be working with OneSpin, the leader and innovator in formal verification. OneSpin’s LaunchPad offering has the potential to open new markets to formal verification.”

Anupam Bakshi, president and CEO, Agnisys

“The Herkules consortium focused on the verification challenge with the highest return for SoC design projects: getting individual functional blocks and IP right, first time. … The consortium partner, OneSpin Solutions, has implemented these techniques in its formal verification tool, 360 MV. This new verification approach achieves the heretofore unachievable goal of 100 percent verification by a combination of formal property checking and the automatic detection of verification holes. These are the holes that are all too often not found by other formal verification technologies or by using simulation based upon anticipation.”

Roland Syba, development engineer, Melexis

“Computing hardware fault metrics and achieving targets set by ISO 26262 is challenging, but crucial to enable the application of our massively parallel many-core technology in autonomous vehicles. OneSpin is a trusted provider of apps, methodology and expertise to automate many steps of this process. Working cooperatively with its engineers smoothed our path to ISO 26262, savings months of project time.”

Camille Jalier, director of hardware R&D, Kalray

“We achieved IEC 61508 SIL 4 for the fault avoidance measures during development of the functional safety controller vCOSS S-zero®, a challenging endeavor for this type of equipment. We used a number of technologies to meet SIL 4 requirements, but equivalence verification using OneSpin’s EC-FPGA and EC-RTL was indispensable.”

Masahiro Shiraishi, chief engineer, Hitachi

“You can optionally use the third-party OneSpin 360 EC-FPGA* sequential equivalence checking tool to verify the logic equivalence between specific netlists following compilation. The 360 EC-FPGA software can help you to confirm that aggressive Compiler optimizations do not introduce unexpected results.”

Third-party Logic Equivalence Checking Tools User Guide, Intel

“OneSpin Solutions has created innovative formal-based design verification and equivalence checking solutions that are being used to fully vet some of the most safety critical designs in production today. We believe that by including equivalence checking as part of the design flow, we will better meet our customers’ stringent requirements for high-reliability designs.”

Bruce Weyer, VP and business unit manager, Microsemi

“Results of the application of the FP ABIP as part of the OneSpin FPU App in industrial applications show that corner-case bugs can be unveiled within seconds, and unbounded proof achieved within minutes, even for the multiplication operation. These results were obtained without the use of abstractions or assume-guarantee partitioning.”

Ravi Ram, principal engineer, verification architecture, Xilinx

“The MicroSemi ProASIC3 FPGA is a core component of the Advanced Logic System (ALS), and use of the OneSpin 360 Equivalence Checker is an integral part of our FPGA development process for nuclear safety systems.”

Erik Matusek, safety system platform manager, Westinghouse

“OneSpin 360 DV can identify issues early in the design cycle, when it’s easier and more cost effective to make changes.”

Frank Hsu, senior principal member of technical staff, Maxim

“We were looking for a verification method that significantly increases the performance of our functional verification for the MCU platforms. We selected OneSpin's 360 DV technology because it provides the best solution for our needs for advanced capabilities to enable functional verification during the product deployment phase of platform development in a significantly shorter timeframe than logic simulation. The ease of use of Operational ABV, combined with the capacity and performance of 360 DV, saves significant effort in the Renesas Electronics functional verification flow compared to logic simulation.”

Kazutami Arimoto, general manager system core development division, Renesas

Get in touch!

» Contact