Our flyers provide a high-level overview around our solutions
OneSpin® 360 Design Verification Solutions
The OneSpin 360 Design Verification (DV) product line leverages the most advanced, high-performance formal technology as the basis for a range of verification solutions, from automated design analysis to advanced property checking. Solutions and apps have intuitive, flexible user interfaces and debug capabilities. They are easy to integrate into existing hardware development flows.
OneSpin® 360 EC-FPGA™
The OneSpin 360 EC-FPGA solution ensures that advanced FPGA synthesis optimizations, used to achieve competitive functionality, performance, power consumption, and cost targets, do not introduce functional errors. It supports all sequential synthesis optimizations performed in FPGA design flows. OneSpin 360 EC-FPGA is in use at multiple companies as an accuracy gold standard to test their design solutions.
OneSpin® 360 ISO 26262 FMEDA Solution
OneSpin’s FMEDA automation solution provides a streamlined, predictable path to ISO 26262 compliance. A unique set of apps, leveraging structural analysis, next generation formal engines, and expert functional safety knowledge, enable engineers to break the FMEDA into a series of well-defined, integrated steps forming a complete solution. OneSpin’s safety apps can process the largest automotive chips and support both RTL and gate-level netlist designs.
OneSpin® 360 Trust and Security Solution
The OneSpin 360 Trust and Security Solution complements OneSpin’s long-established Functional Correctness and Safety solutions for assuring IC integrity. The solution leverages intelligent design structural analysis, domainspecific data and expertise, and advanced, dedicated formal engines. These are essential to prove the absence of vulnerable logic in complex SoCs, something not achievable with simulation or emulation approaches.
OneSpin® 360 SystemC/C++ Solution
Simulation-style verification of SystemC high-level synthesis (HLS) code is largely performed by compiling and debugging the design representation linked with a SystemC class library, in a similar fashion to a software test. Due to the limited availability of SystemC verification tools, much of the verification task is performed on the resulting synthesized RTL code, introducing a level of indirection that makes correcting issues complex and time consuming.
