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Formal Verification for SystemC/C++ Designs

By Vlada Kalinic, OneSpin: A Siemens Business

Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. This tutorial, first presented at DVCon Europe explores how these formal techniques can be deployed and provides real-world examples.

As the use of SystemC/C++ has expanded, a number of use-cases have emerged in recent years. These include the use of SystemC/C++ to build abstract algorithmic design code that can be used as an input for high-level synthesis (HLS) tools, for virtual platform models for early software test, to develop configurable intellectual property (IP) blocks, and many others.


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