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In the news

Formal Verification for SystemC/C++ Designs

By Vlada Kalinic, OneSpin: A Siemens Business

Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. This tutorial, first presented at DVCon Europe explores how these formal techniques can be deployed and provides real-world examples.

As the use of SystemC/C++ has expanded, a number of use-cases have emerged in recent years. These include the use of SystemC/C++ to build abstract algorithmic design code that can be used as an input for high-level synthesis (HLS) tools, for virtual platform models for early software test, to develop configurable intellectual property (IP) blocks, and many others.

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5 Talks on RISC-V

By Milos Tomic, Veriest

Veriest recently hosted a webinar focusing on RISC-V as a forerunner of ongoing open-source revolution in chip design. Speakers were distinguished professionals from industry and academia. Webinar covered topics from market trends to open-source hardware initiatives, tools and methodologies.

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Continuous Verification

By John Hallman, OneSpin: A Siemens Business

The recent SolarWinds hacking incident that left many fortune-500 companies and US government networks exposed is a cautionary tale for unchecked software and hardware supply chain security vulnerabilities.

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Debugging Embedded Applications

By Ann Steffora Mutschler, Semiconductor Engineering

Software and hardware interdependencies complicate debug in embedded designs. New approaches are maturing to help reduce debug time.

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High-Level Synthesis For RISC-V

By Brian Bailey, Semiconductor Engineering

Abstraction is the key to custom processor design and verification, but defining the right language and tool flow is a work in progress.

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The Road To Osmosis

By Rob van Blommestein, Head of Marketing, OneSpin: A Siemens Business

Sharing information and pushing the boundaries of formal verification.

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