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High-Level Synthesis For RISC-V

By Brian Bailey, Semiconductor Engineering

Abstraction is the key to custom processor design and verification, but defining the right language and tool flow is a work in progress.

High-quality RISC-V implementations are becoming more numerous, but it is the extensibility of the architecture that is driving a lot of design activity. The challenge is designing and implementing custom processors without having to re-implement them every time at the register transfer level (RTL).


Assessing extensions is a different level of architectural optimization that involves software. “You need to figure out the ‘right’ custom instructions for the specific target application so that certain goals can be achieved, be it memory, power, performance, or area,” says Sven Beyer, product manager for OneSpin, a Siemens Business. “To do that, high-level models are needed, like virtual prototypes with custom instructions, running software to assess memory usage or performance. Once the custom extension candidates are identified, they need to be implemented in RTL to allow for the final assessment of key performance indicators (KPI). This task is very tedious when manually writing RTL, even if just adding to an existing RTL core, and manually writing independent prototypes. Keeping the models in sync is challenging.”


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