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Interconnect Challenges Grow, Tools Lag

By Brian Bailey, Semiconductor Engineering

More data, smaller devices are hitting the limits of current technology. The fix may be expensive.

Interconnects are becoming much problematic as devices shrink and the amount of data being moved around a system continues to rise. This limitation has shown up several times in the past, and it’s happening again today.


Most verification tools are ill-suited to the task. “Functional verification of the interconnect fabric is one of the hardest challenges of today’s big SoCs,” says Sergio Marchese, technical marketing manager for OneSpins Solutions. “With the number of connections reaching the order of hundreds of thousands, connectivity verification must be fully automated with solutions of adequate capacity and usability. Moreover, engineers can use plug-and-play apps and VIPs to find corner-case bugs in the various interface protocols used in the interconnect. But more is needed to ensure absence of high-level issues, like deadlocks and livelocks, something that simulation and emulation cannot achieve. With security IPs and features bringing additional complexity to the interconnect, the need to go beyond use-case scenarios verification and towards exhaustive, formal-based, verification is even stronger.”


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