Technical videos

Let our experts guide you through our IC integrity solutions.

Keys to Early Detection of Security Vulnerablities

In this webinar, OneSpin: A Siemens Business and Methodics IPLM by Perforce will demonstrate early security verification on a small module of intellectual property (IP) intended for integration into an IC. Using Methodics IPLM by Perforce’s key technology for IP management and OneSpin 360™ formal verification tools, our technical experts will jointly perform the process recently released for public comment in the Accellera Secure Annotation for Electronic Design Integration (SA-EDI) Standard.

Keys to Early Detection of Security Vulnerablities

What Can I Expect To Learn:

Insight into the Accellera Secure Annotation for Electronic Design Integration (SA-EDI) Standard
Where to find accessible information on security weaknesses and vulnerabilities
As an IP provider:
- How to define a security asset in your design
- How to provide security information on your IP that may be used by customer
As an IP integrator (e.g., SoC designer):
- An understanding of the security protections required for a procured IP
- How formal properties are used to achieve security objectives, including real-world examples
- How to manage security attributes with an IP

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Equivalence Checking for FPGAs

Systematic design errors introduced by synthesis or automated design refinement tools, or Trojan logic inserted by malicious actors, can be hard to detect and damaging if they make it into the final device. Using formal equivalence checking technology that has been used for ASIC design flows for many years, FPGA engineers can now exhaustively verify critical system components in their register transfer level (RTL) code to synthesized netlists and the final placed-and-routed FPGA designs, using an automated flow that is tightly integrated into the FPGA vendors’ platforms. The benefits: accelerated design time, higher design performance from aggressive optimizations, reduced lab time, dramatically smaller post-production risks.

Equivalence Checking for FPGAs

The Equivalence Checking for FPGA on-demand recording session will:

outline the differences between formal verification and simulation in the context of equivalence checking
define the verification challenges for sequential optimizations
discuss the advantages of a step netlist verification approach and related applications
present further related tasks that can be targeted using an equivalence checking verification flow

What You Will Learn:

The need of equivalence checking for FPGAs
Methodologies to apply equivalence checking
The advantages and challenges of stepwise netlist verification

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How to Start Securing Your IC, Section 1: Introduction to Trust and Security Fundamentals

Presented by Product Manager John Hallman, OneSpin’s trust & security overview webinar is a primer course on the ins and outs of hardware security that will leave you with the knowledge and confidence to start addressing this essential piece of your company’s design puzzle.

How to Start Securing Your IC, Section 1: Introduction to Trust and Security Fundamentals

Section 1 introduces the many arms of security. We’ll start with the basics, such as common terminology and industry standards in the security realm. Building on that context, you’ll gain insight into how to identify vulnerabilities in your IC and determine what to protect and prevent in your design.

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How to Start Securing Your IC, Section 2: Getting Started with OneSpin for Trust and Security

Presented by Product Manager John Hallman, Section 2 of OneSpin's trust & security webinar delves into your design verification methodology, which now has security in mind from the very beginning. You’ll learn how to get started in modifying your verification plan and flow to address security challenges at every level. Included is an overview of how OneSpin tools build confidence that your IC is secure.

How to Start Securing Your IC, Section 2: Getting Started with OneSpin for Trust and Security

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OneSpin Ask Me Anything - Episode 3

Martin Rowe answers the question "What makes OneSpin Unique?"

OneSpin Ask Me Anything - Episode 3

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OneSpin Ask Me Anything - Episode 2

Martin Rowe answers the question "What do you recommend for new formal adopters?"

OneSpin Ask Me Anything - Episode 2

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OneSpin Ask Me Anything - Episode 1

Martin Rowe answers the question "What are some of the key benefits of a verification flow that includes formal?"

OneSpin Ask Me Anything - Episode 1

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OpenHW TV: CORE V CVE4 Functional RTL Freeze Milestone

Sven Beyer, Design Verification Product Manager at OneSpin Solutions, joins Episode 5 of OpenHW TV to discuss RISC-V Core verification and RTL Freeze

OpenHW TV: CORE V CVE4 Functional RTL Freeze Milestone

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RISC-V Q&A Session

We've asked the RISC-V community about their most pressing questions and turned to our verification experts to answer them.

Accelerating FPU Verification

Sergio Marchese, Technical Marketing Manager

Speeding Up FPGA Development

Salaheddin Hetalani, Field Application Engineer

Speeding Up FPGA Development

Salaheddin Hetalani, field application engineer at OneSpin Solutions, talks about why it’s getting harder to design and debug FPGAs, how much design time can be saved through formal techniques, and why just relying on programmability isn’t the most efficient approach.

Speeding Up Verification Using SystemC

Brett Cline, VP of Sales

Speeding Up Verification Using SystemC

Brett Cline, senior vice president at OneSpin Solutions, explains how adding formal verification into the high-level synthesis flow can reduce the time spent in optimization and debug by about two-thirds, why this needs to be done well ahead of RTL, starting with issues such as initialization, memory out of bounds and other issues that are difficult to find in simulation.

Formal Verification by the Book

Keerthikumara Devarajegowda, Infineon Technologies

Formal Verification by the Book

Keerthikumara Devarajegowda, PhD candidate at Infineon Technologies, talks about the verification of error correction codes using formal verification, namely OneSpin 360 DV.

Ensuring Coverage In Large SoCs

Sven Beyer, Product Manager Design Verification

Ensuring Coverage In Large SoCs

Sven Beyer, product manager for design verification at OneSpin Solutions, talks with Semiconductor Engineering about why formal technology is required to ensure coverage in some of the newest chips, how it deals with potential interactions and different use cases, and why it is gaining traction in automotive applications.

Finding Hardware Trojans

John Hallman, Product Manager

Finding Hardware Trojans

John Hallman, product manager for trust and security at OneSpin Technologies, talks with Semiconductor Engineering about how to identify hardware Trojans in a design, why IP from different vendors makes this more complicated, and how a digital twin can provide a reference point against which to measure if a design has been compromised.

Safety-Critical Coverage

Dave Landoll, Solutions Architect

Safety-Critical Coverage

Dave Landoll, solutions architect at OneSpin Solutions, discusses verification in safety-critical designs, why it’s more of a challenge in automotive than in avionics, and why verification of these systems includes what the system should not be doing as well as what it should be doing.

Billion-Gate Design Connectivity

Sasa Stamenkovic, Senior Field Application Engineer

Billion-Gate Design Connectivity

Sasa Stamenkovic, senior field application engineer at OneSpin Solutions, explains how to find and resolve connectivity issues in integrating large numbers of components in very big designs, often at the leading-edge nodes and in markets such as AI.

Heterogeneous Computing Verification

Raik Brinkmann, CEO and President

Heterogeneous Computing Verification

Raik Brinkmann, CEO of OneSpin Solutions, looks at new architectures involving AI and machine learning, what changes in these multi-accelerator, multi-memories designs, and where problems can crop up both in design and verification.

Planning Out Verification

Nicolae Tusinschi, Product Specialist Design Verification

Planning Out Verification

Nicolae Tusinschi talks with Semiconductor Engineering about how to move from specification to signoff in a verification flow.

ISO 26262 Statistics

Jorg Gosse, Product Manager Functional Safety

ISO 26262 Statistics

Jorg Gosse, functional safety product manager at OneSpin Solutions, talks with Semiconductor Engineering about the statistics behind the standards, what is considered good enough, and how those numbers vary across different standards.

Traceability In Functional Safety

Dominik Strasser, Vice President of Engineering

Traceability In Functional Safety

Dominik Strasser, vice president of engineering at OneSpin Solutions, talks with Semiconductor Engineering about the impact of functional safety regulations on liability and traceability in automotive, rail, industrial, nuclear and machinery applications.

Nicolae Tusinschi on Floating-Point Units

Nicolae Tusinschi, Product Specialist Design Verification

Nicolae Tusinschi on Floating-Point Units

Nicolae Tusinschi about Formal Verification of Floating-Point Hardware with Assertion-Based VIP.

FPGA RTL Checking

Tobias Welp, Product Owner and Engineering Manager

FPGA RTL Checking

OneSpin's Tobias Welp talks with Semiconductor Engineering about how to ensure the RTL created by design engineers matches what shows up in an FPGA.