Enabling The RISC-V Ecosystem
Industry initiatives are critical factors for processor family success.
Tom Anderson, Technical Marketing at OneSpin
Earlier this year, OneSpin’s Sven Beyer discussed the emerging RISC-V processor and some of its verification challenges. He stated that “RISC-V is hot and stands at the beginning of what may be a major shift in the industry.” In the few intervening months, it has become even more apparent that RISC-V is fundamentally changing system-on-chip (SoC) development. Dozens of commercial and open-source implementations of processor cores are available, and millions of SoCs have already shipped with embedded RISC-V processors. Two industry groups have been established to promote RISC-V and help grow the ecosystem of hardware, software, tools, and services.
For this post we’re taking a step back from the technical details to discuss these activities and the role that OneSpin is playing.
Like previous generations of reduced instruction set computer (RISC) designs, RISC-V has its roots in academia. The project to develop a fifth-generation RISC-based instruction set architecture (ISA) began in 2010 at the University of California at Berkeley. As with previous RISC projects both academic and commercial, the goal was to define an ISA enabling small, fast designs with the potential for low-power operation when needed. Unlike some of those other projects, the intent was for RISC-V to support a wide variety of diverse implementations. This required the ISA to have the flexibility to map to many different microarchitectures with different power, performance, and area (PPA) tradeoffs appropriate for targeted end applications.
In 2015, the RISC-V Foundation was established to own, maintain, and publish the ISA and related documents. Original RISC-V authors and developers surrendered their rights to the foundation. There are now nearly 250 members, spanning universities, semiconductor suppliers, system houses, software vendors, and IP providers. The Foundation ensures that RISC-V remains open as per the original vision of its developers. This openness is a sharp contrast to the proprietary ISAs that have dominated computing for decades and has at least three dimensions. First, the RISC-V ISA has been developed and evolved by a wide circle of collaborators from both industry and academia. Anyone can contribute ideas and participate in the discussions, although the ability to vote is reserved for members of the Foundation, which anyone can join.
Similarly, anyone can develop and market hardware or software products based on the ISA with no licensing or royalty fees, although only members may use the group’s official logo. Finally, there are numerous open-source RISC-V processor and SoC implementations available that anyone can download and use, again with no licensing or royalty fees. The Foundation maintains a list of these designs and the repositories where they reside, but does not directly offer, support, or endorse any open-source (or commercial) implementations. There is a working group chartered to develop an ISA compliance test suite, but at this time the Foundation does not offer any sort of certification services. The Foundation also maintains a list of software related to RISC-V development and usage.
Open-source cores are useful for those who want to explore RISC-V and see if the processor family might be a good fit for a particular SoC project. However, when it comes time to actually build a chip using RISC-V, many developers will want some evidence that the core is fully compliant with the ISA. For this reason, the OpenHW Group was established and announced just a few weeks ago. Its mission includes “providing a platform for collaboration, creating a focal point for ecosystem development, and offering open-source IP for processor cores.” The goal is to remove barriers to the adoption of open-source cores by ensuring quality with best-in-class design and verification contributions from the community. The OpenHW Group also announced CORE-V, a family of RISC-V based open-source cores with associated processor subsystem IP, tools, and software.
Where does OneSpin fit into all this? For a start, we joined the RISC-V Foundation and are a founding member of the OpenHW Group. Although OneSpin is an active member of both organizations, we do not presume to speak for either in this blog post. We encourage you to visit their sites and learn more about them in their own words. From our perspective, the two initiatives are complementary in their goals and missions. The RISC-V Foundation will maintain and evolve the ISA and other key documents while the OpenHW Group will provide high-quality RISC-V open-source implementations. We have a vested interest in the success of both organizations and are devoting significant resources to help grow the RISC-V ecosystem.
Our goal is to offer products and services that enable design integrity for RISC-V cores and the SoC that integrate them. This means verifying functional correctness, ensuring proper operation in safety-critical applications, checking to be sure that any design is secure and trusted, free of unintentional or deliberate vulnerabilities, and establishing proof of compliance to the ISA. We recently announced our RISC-V Verification App, the first component of our overall RISC-V Integrity Solution. We’re looking forward to expanding our offerings while we work with leading-edge customers and share our expertise with the community through both organizations. RISC-V has great promise, and OneSpin will be a key player in making it wildly successful.
About the author
Tom Anderson is technical marketing consultant at OneSpin Solutions. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.