Ensuring key connectivity through SoC communication structures
The wiring of multiple functional blocks through the hierarchical layers of a design is a tedious and error prone task. Errors in signal naming conventions, switched positions in port lists, incorrectly matched bus bit positions, and many other fault conditions produce seemingly simple errors that can waste hours of time if undetected until later in the engineering process. Tracking these issues down using simulation is unreliable and cumbersome, as the stimulus used must cover every connection style and behavior in an exhaustive fashion. On accession, connectivity issues can be missed completely, resulting in an expensive device re-spin.
The OneSpin Connectivity Checking app provides an easy to use, automated mechanism to exhaustively verify design connectivity through SoC communication structures.
The SoC Connectivity Problem
The connectivity checking problem outlined above is further compounded by modern interconnect structures. Complex bus protocols with transaction-level signal propagation, Network-on-Chip (NoC) channels, crossbar and bus bridges, for example, mask signal connections throughout a system, making the verification of correct device connectivity hard and time-consuming to establish.
Connection behavior also requires testing, for example, connectivity during reset and power domain switching, a device placed into a test configuration that switches connectivity, and connection options based on control register values.
Specialized tools may also be used to automatically establish connections and this process also requires verification.
Tracking these issues down using simulation is unreliable as the stimulus used must cover every connection style and behavior in an exhaustive fashion, ensuring linkage through complex interconnect structures throughout the design. The creation of such a test set is also time-consuming and error-prone.
Formal Connectivity Checking with OneSpin
The OneSpin Connectivity app, included in the OneSpin 360 DV Verify™ product, takes a range of machine-readable formats such as connectivity specifications and tables (including spreadsheets) as input and generates interconnect assertions. These assertions validate connections through the most complex of design structures. The app also takes the design as input and runs these generated assertions through a formal proof engine to provide an exhaustive test of all interconnects listed in the table.
Conditional, and delayed connections may also be included in the specification tables and verified automatically. This allows for configurable connections to be verified, even when the connection is gated and controlled through register settings, or potentially overridden through device reset or similar occurrences.
If an issue is found with a connection, a simulation trace is generated that highlights the problem to allow its inspection within the included debug system. This waveform trace highlights issues regardless of the connection mechanism, allowing for hard to understand connection problems to be observed.
With this automated formal app, it is now possible to quickly ensure that a complete system platform is wired correctly with virtual connections evaluated, eliminating one of the most common reasons for project delays and faulty silicon.