Eliminates Tool Qualification Effort for Users Targeting Functional Safety Standards ISO 26262, IEC 61508, EN 50128
MUNICH and SAN JOSE, CALIF. – February 14, 2018 – OneSpin® Solutions, provider of innovative formal verification solutions for highly reliable, digital integrated circuits (ICs), today announced successful completion of a series of factory inspections and audits of its organization and tool development processes by internationally-recognized testing body TÜV SÜD. This conformance level enables OneSpin to provide certified formal verification solutions meeting tool qualification requirements set by functional safety standards (ISO 26262, IEC 61508 and EN 50128/SIL 3). As a…
Users Deploy EC-FPGA Formal Sequential Equivalence Checking into Automotive ASIL D Projects with no Additional Tool Qualification Requirements
MUNICH and SAN JOSE, CALIF. – February 14, 2018 – OneSpin® Solutions, provider of innovative formal verification solutions for highly reliable, digital integrated circuits (ICs), announced immediate availability of its OneSpin 360 ECFPGA ™ Tool Qualification Kit certified by internationally-recognized testing body TÜV SÜD. The certification states that EC-FPGA meets the most stringent tool qualification criteria set by functional safety standards ISO 26262 (TCL3/ASIL D), IEC 61508 (T2/SIL 3) and EN 50128 (T2/SIL 3).
Sets Goals to Increase WWED’s Visibility, Promote Vibrant, Supportive Community of Women within Semiconductor Industry
SAN JOSE, CALIF. – October 4, 2017 – McKenzie Ross, marketing communications manager for OneSpin® Solutions, provider of innovative formal verification solutions for highly reliable, digital integrated circuits (ICs), will reprise her role as chair of the Worldwide Women in Electronic Design (WWED) Steering Committee for 2017–2018.
Ross has led the WWED Steering Committee since 2016 and served as vice chair in 2015. In addition to selecting and promoting a female speaker for the Design Automation Conference (DAC), the steering committee works to increase WWED’s visibility…
Formal System Verification Covers State-of-the-Art, Future Trends in Formal Verification
SAN JOSE, CALIF. – September 6, 2017 –OneSpin® Solutions, provider of innovative formal verification solutions for highly reliable, digital integrated circuits (ICs), today announced that its Chief Executive Officer Dr. Raik Brinkmann and Dave Kelf, vice president of marketing, contributed a semiconductor industry perspective to Formal System Verification.
Springer Publishing’s newly released book edited by Dr. Rolf Drechsler, professor of Computer Architecture at the University of Bremen in Bremen, Germany, provides readers with a comprehensive introduction to the formal verification of hardware…
Winning Entry from Nokia's Wolfgang Roessel, Runners Up from Infineon, ARM
SAN JOSE, CA - Jul 27, 2017 -OneSpin® Solutions, provider of innovative formal verification solutions for highly reliable, digital integrated circuits (ICs), today announced Wolfgang Roessel of Nokia provided the winning entry to OneSpin's Einstein's Riddle challenge, based on a public poll of the top 10 solutions.
Runners up are Darren Galpin from Infineon, Laurent Arditi at ARM and Phani Kumar Peri of Infineon.
OneSpin issued a challenge to solve the classic Einstein's Riddle using any formal verification tool. Entries were narrowed down to 10 and OneSpin confirmed they executed correctly using its DV-Verify™…
Random Fault Verification Supported by New Safety Critical Apps, Certification Kits
SAN JOSE, CA - May 31, 2017 -OneSpin® Solutions, provider of innovative formal verification solutions for highly reliable, digital integrated circuits (ICs), today unveiled its comprehensive safety critical analysis and diagnostic coverage solution for automotive and other mission-critical applications.
"While formal verification is invaluable for any hardware application, its ability to debug automotive and mission-critical applications may prove to be the most effective use of this technology," says Dr. Raik Brinkmann, OneSpin's chief executive officer. "OneSpin's formal verification solutions ensure…
At each stop, OneSpin will demonstrate its four comprehensive design verification solutions -- Quantify™ Fault Observation Coverage, SystemC/C++ Formal Verification Environment, Equivalence Checking-Field Programmable Gate Array (EC-FPGA) and Safety Critical Analysis and Diagnostic…
Co-Sponsor of I LOVE DAC Named to Gary Smith EDA’s Must See@DAC List
SAN JOSE, CALIF. –– June 1, 2016 –– OneSpin® Solutions, deemed a “must see” exhibitor at the Design Automation Conference (DAC) by Gary Smith EDA, will showcase its entire line of innovative formal verification solutions for error-free digital integrated circuits (ICs) in DAC Booth #1249.
Additionally, OneSpin will use DAC to unveil its new corporate identity that includes refreshed branding, logo and website. The DAC Exhibit Floor will be open Monday, June 6, through Wednesday, June 8, from 10 a.m. until 6 p.m. at the Austin Convention Center in Austin, Texas.
“In the last four years, OneSpin has grown from a small…
Online Resource Designed to Serve Formal Verification Engineering Community
DVCon 2016 –– SAN JOSE, CALIF. –– February 29, 2016 –– FormalWorld.org, is an online community dedicated to advancing the widespread use of formal verification. Launched today during DVCon 2016 here, the goal of the website is to be a complete online resource for the expanding formal verification community.
Formal verification has become a critical technology in the modern verification flow. With an increasing number of end-users in need of education, information and peer-to-peer networking, the site provides easy, open access to a range of helpful resources.
FormalWorld.org will provide links to a broad range of…
Enables Early Bug Detection During Code Editing For FPGA, ASIC Designers
February 9th, 2016 –– OneSpin® Solutions, provider of innovative formal verification solutions, and Sigasi®, provider of hardware description language (HDL) design software, today announced the integration of the OneSpin formal-based design inspection software with Sigasi’s HDL authoring system Sigasi Studio XL.
The solution gives designers a way to run formal-based structural code checks within Sigasi’s environment at the point of edit, spotting issues that otherwise require additional verification effort. The use of formal techniques eliminates much of the false error-reporting characteristic…