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In the news

Debug: The Schedule Killer

By Brian Bailey


Time spent in debug is unpredictable. It consumes a large portion of the development cycle and can disrupt schedules, but good practices can minimize it.


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Verification Requirements for SystemC/C++ Designs

By Vlada Kalinic, SystemC Verification, Product Manager, OneSpin Solutions

Although SystemC/C++ coding styles have been used for many years, specific models have recently emerged to drive common design flows across engineering teams. These include abstract algorithmic design code as input for high-level synthesis (HLS) tools, virtual platform models for early software test, configurable intellectual property (IP) blocks, and many more.

HLS, which transforms “mostly untimed” abstract SystemC/ C++ design representations to fully-timed register-transfer-level (RTL) design blocks, is in use at many large semiconductor and electronic systems companies. These tools are particularly popular as a method to rapidly generate design components with varying microarchitectures, whilst rapidly and effectively optimizing algorithm-processing data paths. Their use on control logic, as well as components with more detailed timing in general, is also becoming more widespread.

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Precision: A Case Study For Success

By Rob van Blommestein, OneSpin Solutions

Recently, I was watching a documentary on the NASA Perseverance mission to Mars. I’ve always been fascinated by space travel and the engineering efforts to make it happen. We’ve all heard that the landing for this trip to Mars was the most precise in history, but what the documentary brought to light is the precision involved in each and every aspect of the Perseverance Rover design and development.

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