ブロックからチップまで、フォーマル技術を使用した厳密なカバレッジドリブン検証

OneSpin 360 DV-Inspect™ takes designer’s pain away and automatically and exhaustively analysis RTL source code prior to functional verification and synthesis, eliminating hard to find implementation errors early in the design process.

OneSpin 360 DV-Verify™ goes beyond that by providing a unified, coverage-driven assertion-based verification flow, and including a full verification app library, as well as means for easy design exploration, all in one tool.

OneSpin 360 EC-RTL is an easy to use Sequential Equivalency Checking tool that to ensures functional equivalence between RTL design revisions.

360 EC-FPGA is an automatic sequential equivalence checking tool that provides a fast and efficient method to ensure that aggressive synthesis optimizations have not introduced systematic errors that could disrupt the final design.

OneSpin provides a complete set of formal apps as part of OneSpin 360 DV. On top of that, additional innovative capabilities are available, targeting for example safety critical design, or hardware security as special apps and from third party providers.

OneSpin 360 DV-Verify™ goes beyond that by providing a unified, coverage-driven assertion-based verification flow, and including a full verification app library, as well as means for easy design exploration, all in one tool.

The OneSpin 360 Design Verification (DV) product line leverages the most advanced, high-performance formal technology as the basis for a range of verification solutions, from automated design analysis to advanced property checking.

The OneSpin 360 EC-FPGA solution ensures that advanced FPGA synthesis optimizations, used to achieve competitive functionality, performance, power consumption, and cost targets, do not introduce functional errors.

OneSpin 360 DV-Verify extends the DV- Inspect platform with coverage-driven Assertion-Based Verification (ABV). Many entry-level formal apps allow for assertion generation for specific problems without a need for deep formal knowledge.

360 DV-Inspect automatically inspects the RTL code once it has been compiled, without the need for any testbench setup.

The OneSpin 360 EC-FPGA™ solution ensures that advanced FPGA synthesis optimizations, used to achieve competitive functionality, performance, power consumption, and cost targets, do not introduce synthesis and optimization errors.

OneSpin® 360 EC-FPGATM is an automatic sequential equivalence checker that prevents field programmable gate array (FPGA) design flows from introducing synthesis, place-and-route and other implementation errors.

This white paper presents an implementation signoff flow proving that the final FPGA netlist is functionally equivalent to the RTL model. Based on FPGA-specific, mature formal verification technology, the solution is exhaustive and efficient, catching many issues before synthesis starts.

"We had a positive experience in adopting formal verification within a RTL development process that implemented Agile-recommended practices in a localized, low-risk fashion. This approach appears to be an effective and pragmatic way to improve the RTL development process by harnessing some of the benefits of Agile." Sergio Marchese, Verification consultant at TeraStatic.

"The incremental approach allows for feedback between teams far, far sooner than would typically happen using a waterfall approach. The feedback exchanged between teams that are working toward the same goals simultaneously gives many more opportunities to clarify design intent and holds far less potential for long schedule slips." Neil Johnson, Principal Consultant – XtremeEDA Corp., Bryan Morris, VP Engineering – XtremeEDA Corp.

"Agile development techniques are now sweeping through the software community transforming the way we develop software. But apart from a few isolated reports the hardware community has been largely untouched by this revolution." François Cerisier and Mike Bartley, Test and Verification Solutions.

"While there are obvious differences between software development and hardware development, there are also significant similarities. The key for hardware developers is to resist getting caught up with the differences and to instead focus on the similarities. Doing so makes it hard to argue that the values of the agile manifesto and agile practices could not be used to achieve the same benefits that software developers have been realizing for years." Neil Johnson, Principal Consultant at XtremeEDA Corp.

We are uncovering better ways of developing software by doing it and helping others do it. Through this work we have come to value:

Muhammad Haque Khan, product specialist for Synthesis Verification, is speaking about our FPGA-specific, mature formal verification technology, that is exhaustive and efficient, catching many issues before synthesis starts.