Technical Deep Dive: Assuring the Integrity of FPGA Designs
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Abstract: Part 1: Avoid Systematic Design Errors from Synthesis Optimization
Systematic design errors introduced by automated design refinement tools, such as synthesis, can be hard to detect, not to mention damaging if they make it into the final device. Formal equivalence checking has been used for ASIC design flows for many years. As FPGAs become bigger, critical system components, exhaustively verifying the functional equivalence of register transfer level (RTL) code to synthesized netlists and the final placed-and-routed FPGA designs is mandatory.
Part 2: Overcome Obsolete FPGA Technology to Achieve Design Continuity
Many designs targeted to obsolete FPGAs are still functionally viable, but old FPGAs are no longer available to support the design or acquiring these obsolete FPGAs is cost prohibitive. The time, resources, and cost of redesigning onto newer FPGAs may not be practical. Re-synthesizing the RTL to meet the desired new technology may also not be feasible: there are many pitfalls associated with this process that can lead to errors finding their way into the design. Adding to the dilemma is the fact that new FPGA technology offers significant benefits that obsolete technology doesn’t have in terms of safety, security, trust, and power-saving features, while designs on obsolete technology can be inadequate to meet the stringent demands of today’s market. Retargeting these designs to newer FPGA technology extends the life of designs and ensures that designs are brought up to the latest safety and security standards while reducing power consumption.
