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IC Integrity Verification Content a Focus at Industry Virtual Conferences – Tackling Functional Correctness, Safety, Trust and Security

By: Rob van Blommestein, Head of Marketing 

We’re six months into the pandemic, and it looks like in-person conferences are becoming a distant memory and that virtual conferences are now becoming routine. It used to be that traveling to a conference (sometimes long distances) was the only way to be able to attend technical presentations and learn about the latest technologies and methodologies, and that was only if you received permission from your boss to attend. Travel isn’t cheap and taking extended time away from the office meant that you weren’t spending that time on engineering your company’s products. You were also forced to remember the information or download the PDFs of the proceeding that you could reference. 

Virtual has changed the game in terms of how we are able to access coveted conference materials. The virtual conferences allow anyone from around the world attend without the expense of travel or the time spent away from critical projects. Furthermore, video recordings of presentations are now standard and are available on-demand even after the virtual event has taken place that you can refer to over and over again. 

To that end, OneSpin’s participation at DAC and the upcoming DVCon Europe technical program has given us the unique opportunity to extend our knowledge of IC integrity verification to you in easily digestible formats regardless of your geography. Below are conference materials that you can download that relate to making sure your designs operate as intended and are safe, trusted and secure no matter if you’re working with commercial or open-source cores (such as RISC-V).

57th DAC Content You Can Download Today:

Automated Trustworthiness Assessment of Third-Party Semiconductor IPs

IP Track Paper Presented by John Hallman, Product Manager Trust & Security

Developers of safety- and security-critical SoCs can no longer afford to ignore the risks of security vulnerabilities when integrating third-party IPs. Re-verification of an IP is not feasible, and the cost is prohibitive, even more so when the implementation-level expertise is not in-house. Verification and code reviews are likely to miss stealthy Trojans or vulnerabilities that surface in deep corner-cases, misuse scenarios that are far from the IP intended usage. Some solutions are emerging to address these challenges. The Aerospace Corporation and OneSpin share results of the application of an automated IP trust and assurance flow on over 90 RTL designs.

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Security and Trust Assurance of RISC-V Open-Source Cores

Poster Session presented by Sven Beyer, Chief Scientist, OneSpin Solutions

RISC-V has reinvigorated the open-source hardware community. Many individuals, companies, and organizations, including the OpenHW Group, are continuously releasing new and updated implementations of the RISC-V ISA. However, thorough functional verification of processors is very costly. Established IP providers using proprietary architectures have decades of experience and enormous resources dedicated to functional verification. And yet, security issues are routinely missed. RISC-V makes it possible and affordable to take the assurance and security verification of processor cores to the next level, matching or even exceeding the quality of established IP providers. Edaptive Computing and OneSpin share results of the application of a RISC-V formal verification solution to two cores (RocketCore and OpenHW CV32E40P).

Download the Poster Presentation

Analysis of Faults in Safety Mechanisms and Computation of ISO 26262 Metrics

Poster Session presented by Jörg Grosse, Functional Safety Product Manager, OneSpin Solutions

Quantitative FMEDA for automotive applications and compliance with ISO 26262 can be challenging. Fault injection can be used for deriving hardware safety metrics. However, for complex chips or semiconductor IPs with a variety of safety mechanisms, using fault simulation is laborious and time-consuming. What are the right stimuli to use? How can I speed up fault simulation? How can I detect early in the flow if the safety architecture will not get me to the target SPFM and LFM metrics, whether my goal is an ASIL-B, ASIL-C, or ASIL-D system? The good news is that there are alternative ways to approach the problem that can reduce or even eliminate the need for fault simulation. Discover how to implement a streamlined, automated, and efficient quantitative FMEDA flow.

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The Role of Equivalence Checking for FPGAs in Nuclear Applications

Poster Session presented by Jürgen Dennerlein, Platform Architect & Hardware Developer, Framatome

The IEC SC 45A standard series regulates electronic instrumentation and control equipment in nuclear applications. In particular, IEC 62566 focuses on FPGA development activities, including verification of the post-synthesis and post-place-and-route netlists. How can you reduce the need for slow gate-level simulations? How can you be sure that the implementation tools have not introduced errors? Is that possible when using more advanced implementation flows? Luckily, there are formal verification tools that are dedicated to FPGA flows. Within a few days of effort, it is possible to exhaustive verify large netlists. Crucially, these tools are independent of the implementation tools, an essential requirement from safety standards.

Download the Poster Presentation

Formal Verification of RISC-V Cores

RISC-V Theater Presentation by Salaheddin Hetalani, OneSpin Field Application Engineer

OneSpin is a proud member of RISC-V International and the OpenHW Group. As part of our participation in the Virtual DAC RISC-V Pavilion, FAE Salaheddin Hetalani will give an overview of how formal verification offers critical advantages when it comes to ensuring that designs incorporating open source hardware are free of bugs and other issues. Featured in the presentation are a number of case studies involving successful verifications with OneSpin's RISC-V Verification App, which automates and accelerates verification to ensure proof of compliance to the RISC-V instruction set architecture (ISA) with no gaps or inconsistencies.

Watch the Video

DVCon Europe 2020 Content Not to Miss

Virtual DVCon Europe will be held on October 27 and 28. OneSpin is scheduled to host a couple of paper presentations on the topic of trust and security as well as a tutorial on how to achieve verification coverage for safety signoff and certification. Be sure to check out these sessions!

Paper Presentation

An Automated Pre-silicon IP Trustworthiness Assessment for Hardware Assurance

Integrated circuit designs include in-house and third-party intellectual properties that could contain hardware Trojans. An independent, trusted, and complete IP model, suitable for automated formal comparison with the IP register-transfer level (RTL) code using commercially available tools, may be used to prove absence of functional Trojans. Such models are generally not available, except for certain critical IPs, as, for example, RISC-V processor cores. The development of these models may be costly and time-consuming. This paper proposes an IP trustworthiness assessment process that does not require a trusted model. The approach uses automated tools that scan the IP RTL code to detect suspicious or unusual code patterns and known Trojan signatures. This low-effort, objective assessment may detect Trojans and provide warnings that, depending on the specific project circumstances, may require additional investigation. The approach is demonstrated on numerous open-source and proprietary test designs containing hardware Trojans.

Paper Presentation

A Methodology to Verify Functionality, Security, and Trust for RISC-V Cores
Modern processor designs present some of the toughest hardware verification challenges. These challenges are especially acute for RISC-V processor core designs, with a wide range of variations and implementations available from a plethora of sources. This session describes a common verification methodology available to both RISC-V core providers and system-on-chip (SoC) teams integrating these cores. It spans functional correctness, including compliance, detection of security vulnerabilities, and trust verification that no malicious logic has been inserted. Detailed examples of design bugs found in actual RISC-V core implementations are included. This talk is appropriate for anyone developing or evaluating RISC-V designs.


Beyond Bug Hunting: Verification Coverage from Safety to Certification
Understanding verification coverage is critical for meeting IC integrity standards and goes well beyond detecting bugs in the design. Without proper verification coverage metrics, meeting strict safety standards and certification may not be achievable. Precise metrics indicate where there are gaps in verification and provide a clear view of the progress being made in the verification effort. Common simulation metrics are imprecise and only measure control coverage resulting in significant lack in verification quality. These remedial practices are time-consuming and leave undetected bugs that could significantly impact design safety. Mutation analysis takes the risk out achieving safety signoff. Results and accurate and reproduceable and creates reliable identification of verification gaps by highlighting over-constraining, dead and redundant code. 

This tutorial will explore how mutation analysis can have a positive impact on the safety of your design and provide signoff confidence needed to achieve proper safety certification.

In addition, the tutorial will show how to achieve a meaningful integration of formal and simulation coverage metrics. A long-standing wish of many verification engineers and managers, coverage integration reduces effort overlap between simulation and formal, and enables faster, more rigorous signoff. 

Register for DVCon Europe at

We hope that the information crafted by our team of experts will help you in your efforts to achieve IC integrity!