Heterogeneous Computing Raises The Bar For Functional Verification
By Raik Brinkmann, Semiconductor Engineering
Programmable SoCs are shaping up to be an important part of the semiconductor landscape, if they can overcome the verification challenges.
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If there’s one thing certain in chip development, it’s that every innovation in architecture or semiconductor technology puts more pressure on the functional verification process. The increase in gate count for each new technology node stresses tool capacity. Every step up in complexity makes it harder to find deep, corner-case bugs. The dramatic growth in SoC designs brings software into play for full-chip verification. True to form, the emerging generation of heterogeneous computing platforms is raising the bar for verification yet again. This new approach presents new challenges that must be faced by both device developers and chip users.
The term “heterogeneous” may not at first sound too daunting, since SoCs have for some time included multiple forms of processors. Traditional CPUs have blossomed into multiprocessor subsystems while GPUs and other specialized compute engines have also resided on the same chip. But heterogeneous computing takes this architecture two steps further by also including both FPGA-style programmable logic and software-programmable engines. These features greatly increase the flexibility available to users to implement their desired functionality in hardware, software, or a combination of both.
