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OneSpin Blog

High-Level Design and High-Level Verification

Expectations for C++/SystemC Designs Must Be Set Properly

By Dominik Strasser, Vice President of Engineering

Not so long ago, some EDA vendors were painting a very attractive picture of chip design in the then-near future. The idea was that an architectural team would write a single description of the complete system in some high-level language, usually C/C++/SystemC, and that a new class of EDA...

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Chip Security Needs A New Language

SystemVerilog assertions can nicely capture many hardware requirements. However, more is needed for security verification.

By Sven Beyer and Sergio Marchese

Safety- and security-critical systems, such as connected autonomous vehicles, require high-integrity integrated circuits (ICs). Functional correctness and safety are necessary to establish IC integrity, but not sufficient. Security is...

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A Holistic View Of RISC-V Verification

Successful projects entail more than core compliance to the ISA.

By Nicolae Tusinschi, Product Specialist Design Verification, OneSpin

Last month, we discussed the growth of the RISC-V open processor ecosystem, the two main organizations driving it, and the role that OneSpin plays. In addition, we have become very active in the RISC-V community and have more than a dozen technical articles...

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Enabling The RISC-V Ecosystem

Industry initiatives are critical factors for processor family success.

Tom Anderson, Technical Marketing at OneSpin

Earlier this year, OneSpin’s Sven Beyer discussed the emerging RISC-V processor and some of its verification challenges. He stated that “RISC-V is hot and stands at the beginning of what may be a major shift in the industry.” In the few intervening months, it has become even more...

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Intellectual Property: Trust… But Verify

As the supply chain of components and IP expands, so too do the opportunities for adversarial tampering.

By John Hallman, Product Manager Trust & Security

For those around the microelectronic component industry for many years, we have seen quite a transformation of capability, sourcing of the supply chain, and now threats to these devices that drive the technology in our world today.

These...

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Hardware Trojans And The Problem Of Trust In Integrated Circuits

IC development steps are vulnerable to malicious insertions that may compromise system security.

By Sergio Marchese, Technical Marketing Manager

Electronic systems are at the core of an ever-increasing number of products and services. From power plants to automobiles, from medical devices to airplanes, from smartphones to home appliances, complex electronic systems enable an unprecedented level...

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IC Integrity Thesis

By Jim Hogan, Vista Ventures

Most of my investments are associated with large changes in the semiconductor industry. These changes create opportunities for new and disruptive technologies. I also look to find solutions that provide a compelling reason to adopt a new technology or approach.  When talking about a new approach, it often takes longer to overcome the status quo.

In this thesis, I...

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Fibonacci And Honey Bees Have Something In Common: A Sweet Spot For Formal

Can assertions enable engineers to design IP that is correct by construction?

By Sergio Marchese, Technical Marketing Manager

Time flies and the OneSpin’s Holiday Puzzle tradition has reached its third year. In December 2016, OneSpin challenged engineers everywhere to solve the Einstein riddle using assertions and a formal verification tool. In December 2017, the challenge was to model the harde...

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Formal Verification Of RISC-V Cores

By Sven Beyer, Product Manager Design Verification

RISC-V is hot and stands at the beginning of what may be a major shift in the industry. Even a cursory review of upcoming conferences programs and recent technical articles makes that clear. While it is still early in the evolution of the processor architecture, there is certainly the potential that RISC-V will be a game-changer in the IP and...

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Connectivity Checking Is A Perfect Fit For Formal Verification

By Tom Anderson, Technical Marketing Consultant

Formal verification has traditionally been regarded as an advanced technique for experts to thoroughly verify individual blocks of logic, or perhaps small clusters of blocks. However, if you talk to anyone involved in the field these days, you’ll find that the majority of formal users are running applications (“apps”) targeted for specific...

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Heterogeneous Computing Raises The Bar For Functional Verification

By Raik Brinkmann, CEO and President

If there’s one thing certain in chip development, it’s that every innovation in architecture or semiconductor technology puts more pressure on the functional verification process. The increase in gate count for each new technology node stresses tool capacity. Every step up in complexity makes it harder to find deep, corner-case bugs. The dramatic growth in SoC...

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Integrating Results And Coverage From Simulation And Formal

By Tom Anderson, Technical Marketing Consultant

Not so long ago, formal verification was considered an exotic technology used only by specialists for specific verification challenges such as cache coherency. As chips have grown ceaselessly in size and complexity, the traditional verification method of simulation could not keep pace. The task of generating and running enough tests consumed...

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11 Myths About Formal Verification

By Tom Anderson, Technical Marketing Consultant

Formal verification, which uses mathematical analysis rather than simulation tests, has been available in commercial EDA tools for more than 20 years and in academia much longer. As with many new technologies, initial adoption was slow and limited to companies who had in-house formal experts. This has changed dramatically in the last dozen years or...

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AI Chips Must Get The Floating-Point Math Right

By Sergio Marchese, Technical Marketing Manager

Most AI chips and hardware accelerators that power machine learning (ML) and deep learning (DL) applications include floating-point units (FPUs). Algorithms used in neural networks today are often based on operations that use multiplication and addition of floating-point values, which subsequently need to be scaled to different sizes and for...

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Demystifying EDA Support For ISO 26262 Tool Qualification

By Sergio Marchese, Technical Marketing Manager

My new, mid-size car is equipped with many advanced driver-assistance systems. To be honest, it’s taking me time to get used to some of them, as, for example, lane-centering assist that seamlessly takes control of my steering wheel. However, I cannot wait to get my hands off a fully autonomous vehicle and be able to take a nap while 7nm chips run...

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Functional Safety: Art Or Science?

By Sergio Marchese, Technical Marketing Manager

Nowadays, most hardware development projects deploy functional verification flows that include UVM-based constrained-random testbenches and formal verification. High design complexity, tough budget constraints, and short time to market are the norm, not the exception. Advanced verification is a necessity for many engineering teams. In our...

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IoT Verification is Harder than it Looks

By Tom Anderson, Technical Marketing Consultant

As has been the case for at least 20 years, functional verification remains the bottleneck for semiconductor development. Many studies have shown that verification consumes 60-70% of a project’s time and resources. As more and more of the chip’s content comes from commercial intellectual property (IP) or reuse from previous generations, the ratio of...

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