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OneSpin featured on Gary Smith's "Must See At DAC" List

Peggy Aycinena inteviews Dave Kelf on OneSpin, Quantify Observation Coverage and DAC. OneSpin will demonstrate Quantify in Booth #1219, June 2nd to 4th, from 9 a.m. until 6 p.m. at Moscone Center in San Francisco.

Are you having problems verifying your ASIC, ASSP, and SoC designs? Are you planning on attending the Design Automation Conference (DAC) this year? If you answered "yes" to both of these questions, then one company that would be well worth your time to visit is OneSpin Solutions.

While most verification standards did not consider formal, they provide a wealth of data that can be mined. Questions still remain about when you have done enough verification.

".. we also have to ask, have enough assertions been written to cover the design properly? If a problem exists in the design, will it be discovered by the assertions? We need to add this type of coverage on top of everything else. .. That addresses the fundamental issue: how do we make formal for the masses?", says Dave Kelf.

Even UVM doesn’t have universal buy-in. Dave Kelf, vice president of marketing for OneSpin Solutions, is not sure we have a firm footing with UVM. “It seems that SystemVerilog coupled with UVM, while considered the right direction for simulation-based flows, is simply too complex for engineers to get their heads around. No doubt a lot of this was due to its origins with multiple large companies pushing their own ideas and, possibly, over enthusiastic committee members with strong opinions not shared by others.”

Semiconductor Engineering sat down with a panel of experts to find out what caused this change and what more we can expect from formal verification technologies in the future. Participating in the panel were Pete Hardee, director of product management for Incisive Formal at Cadence; Oz Levia, vice president of marketing and business development at Jasper Design Automation; Pranav Ashar, CTO at Real Intent; Dave Kelf, marketing director at OneSpin Solutions; and Vigyan Singhal, CEO of Oski Technology.

The new Quantify product examines the completeness of the assertions and checkers in the design. The assertions are designed to catch problems during formal verification, but it’s possible to write ineffective assertions. Looked at another way, if assertions are poor or incomplete, then there may be code failures that could never be observed by the assertions.

In the interview Dr. Raik Brinkmann, a co-founder of OneSpin Solutions, was asked about what he thinks about the current state of affairs is in the verification space as well as what trends he sees.

For example, Dr. Raik Brinkmann is considering: "As ever, verification continues to rapidly evolve. Coverage analysis (checking that the design has been fully tested or “covered”) is becoming more and more important as we move toward environments where coverage will drive the verification process. Formal verification is being leveraged more and more, both directly in flows and indirectly as part of other tools and solutions."