close By using this website, you agree to the use of cookies. Detailed information on the use of cookies on this website can be obtained on OneSpin's Privacy Policy. At this point you may also object to the use of cookies and adjust the browser settings accordingly.

In the news

From Tech Design Forum: Linking high-level synthesis with formal verification

High-level synthesis provides a way to explore hardware architectures to come up with the most efficient implementation for a given situation. But it has taken time for verification techniques to catch up with the idea and ensure design and architecture match.

The growth in the use of C++ and SystemC for describing electronic hardware components, particularly at the algorithmic level, has been one of the best-kept secrets in EDA. Although multiple SystemC applications are envisaged –– for example, abstract hardware, virtual platforms and configurable intellectual property (IP) –– the use of SystemC for modeling algorithms and then using them as the input to High Level Synthesis (HLS) tools is becoming much more common.

Read more

From Semiconductor Engineering: Can Cars Be Hack-Proof?

Dave Kelf, vice president of marketing at OneSpin Solutions, has seen this firsthand with automotive companies. “In terms of verification, they have to do what everyone else is doing—but much better. Everyone else can say they can get away with 90% to 95% coverage of the design. These guys have to do 100%, no mucking about. That means that it’s the usual story around verification, but it’s more rigorous.”

Verifying how a chip in the field will operate under varying design conditions with a number of potential faults is a difficult verification problem, he stressed. To this end, OneSpin has been working with other tool providers to determine the best way to build a tool that allows for fault insertion into the design — which cannot be changed — whereby the fault must be inserted on top of the design as it stands, and to see the effect of that on the rest of the design as the fault propagates. “That is a huge EDA problem. So as you find all these unusual design issues you find opportunities for EDA to help figure out solutions for those—on top of the verification guys within the companies are already doing. Security is another one of those.”

Read more


From Semiconductor Engineering: EDA’s Clouded Future

There was a time, not that long ago, when chip design and EDA tools consumed some of the largest data centers with tens of thousands of machines and single datasets that consumed more than a hard disk could hold. The existing IT capabilities of the times were stretched to their limits. But while design sizes grew, other aspects of the flow did not develop as fast.

Read more

From EDA Cafe, The Breker Treker: Rain or Shine for the EDA Cloud?

Recent announcements from IBM and others about supporting EDA tools in the cloud have spurred renewed discussion on this topic, including here at The Breker Trekker. As expected, the recent posts have been very popular with our readers. Those of you who have been following this topic for a while may recall that, almost exactly two years ago, EDA vendor OneSpin announced cloud support for their formal tools. We invited their VP of Marketing, Dave Kelf, to fill us in their experiences since then:

Read more

From The Electronic Engineering Journal: Decoupling Formal Technology from Formal Technology

Formal verification technology appears in the ascendant at the moment. It’s been around forever, it seems, but it’s now finding its way into more flows than ever.

And that’s because users don’t have to deal with formal technology.

The problem with formal is that it’s hard. And, historically, an investment in formal was best matched by an investment in a PhD or two to help out. Or perhaps by hiring some specialist consultants to help out. The way we’ve started to shake off some of those shackles is through apps. The companies making formal technology realized that they had to target specific problems and then bury the formal bits below a user interface and flow that were more natural to the problem being solved.

Read more

From All Electronics: Things can be done more quickly

360-Launch-Pad von Onespin Solutions ist eine anpassungsfähige formale Plattform, die es Drittanbietern ermöglicht, weitere Verifikationsanwendungen (Apps) zu entwickeln, die auf der leistungsfähigen formalen Verifikationstechnologie von Onespin Solutions basieren.

Read more

From The Tech Design Forum: OneSpin brings formal to bear on ISO 26262 fault tracing

OneSpin Solutions has used its formal-verification technology as the basis for an app intended for ISO 26262 projects that analyzes the ability of a design to deal with fault conditions.

Raik Brinkmann, president and CEO of OneSpin, said: “Fault qualification is one of the most time-consuming and important operations in the verification of these designs, and we have produced a unique app that fully complements our safety critical solution.”

Read more

Press Contact

Michelle Clancy
» send an e-mail
» +1 503-702-4732