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In the news

EDA Tackles Functional Safety: New Tools for Safer Designs

by Bryon Moyer, EE Journal

For years, when we have thought “functional safety” or “safety-critical design,” we’ve pictured airplanes, spaceships, and weapons. All of these systems rely on tons of electronics, and they have to work properly or else bad things happen – either lots of time and money lost or lives lost.

And so, for years, the “mil/aero” world has been its own special thing. Some companies specialize in that business because margins can be good. Others stay away because design cycles are long and unpredictable, and there can be tons of paperwork – and who needs that, right?

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Meanwhile, OneSpin has also newly addressed this space. Their approach to dealing with systematic errors harkens back to messaging they were using many years ago: gap-free verification. This gets to the notion that, given a set of design requirements, the design should behave in a way that meets all the requirements and nothing more than those requirements. Every element of the design should be necessary and sufficient. Any behavior that lies outside those specified in the requirements become an issue. So, clearly, this is something that OneSpin has cut its teeth on.

For random errors, however, they have an approach different from – and potentially complementary to – Austemper’s. OneSpin’s Dave Kelf noted that, after simulation-based fault analysis, there typically remain on the order of a couple hundred uncertain faults that need to be checked manually. And real-world speed is such that one can address roughly one such fault per day. But, of course, OneSpin does everything using formal analysis rather than simulation, so this issue goes away.

OneSpin has three applications for handling random errors. FPA starts by pruning non-propagatable faults from future analysis. After all, if a fault occurs and it never gets to or affects an output, did it really happen? Truly navel-gazing stuff, but, from a practical standpoint, time need not be spent on such faults. You could say that such faults are self-handling.

FLA then looks at fault-handling circuits to prove that they work. OneSpin had to add some functionality to their tools to make this second tool work – something that might sound trivial: force and release. Those are, in fact, trivial to do in a simulator, because they’re event-based commands that blend well with a simulation mindset. But they’re not so obvious with formal verification – and yet they were necessary for proving that an injected fault can be handled.

Finally, they have FDA, which quantifies fault coverage. It still requires some time to run – weeks for a large-scale design – but there’s no need to generate scenarios or vectors, as is needed with simulation. And there’s none of the uncertainty and dispositioning that are required for simulated faults, saving literally hundreds of engineer-days.

There’s even some talk with Austemper to see whether a formal engine might be more effective than simulation for Austemper’s Kaleidoscope tool. This is the “complementary” bit that I referred to. It’s not certain whether this will happen, but it shows how different solutions may overlap in constructive ways.

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And The Winners Are… 10 Formal Solutions To Einstein’s Riddle

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By Sergio Marchese, Semiconductor Engineering

A few months back, OneSpin asked engineers to solve the classic Einstein’s Riddle using a formal tool. The challenge became hugely popular, and we received many outstanding solutions. To check out the riddle itself and the top 10 solutions created by leading engineers, click here.

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How Much Verification Is Necessary?

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By Ann Steffora Mutschler, Semiconductor Engineering

“A lot of verification is actually process oriented,” said Ashish Darbari, director of product management at OneSpin Solutions. “It’s about putting the right technology, the right resources, the right stage of the project, and obviously getting the right people involved. The challenges of technology in terms of design are huge. If you thought initially it was Intel’s high performance computing, then low-power came along, and power became the over-arching requirement for design. Now you have safety and security, while power and performance are still there. So the requirements are only increasing.”

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Doc Formal: The evolution of formal verification – Part One

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We celebrate innovation and creativity in the way we cherish fortresses, castles, and other monuments built throughout history. We have always been infatuated with architecture, with the design of the finished structures, even with the process itself, but not with how these buildings were tested. Many books describe how amazing landmarks were built and explain their beauty, but you are unlikely to find much about how they were examined for quality and rigor.

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Automotive Safety Moves Into Semiconductors

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By James Morra, Electronic Design

OneSpin’s thesis is that formal verification is ideal for testing automotive chips. The ISO26262 standard also sets the bar high for safety, requiring that the billions of transistors inside chips be fault-free. To meet another requirement for diagnostic coverage, chips must be 99% protected against environmental effects that could cause, for example, bit flips in memory and accidentally engage the car’s brakes.

"About 10 years ago, everyone realized that simulation didn't have the horsepower anymore," said Dave Kelf, vice president of marketing for OneSpin, in a recent interview. "Now, we are into incredibly complex chips, these simulations run for weeks, and designers would check in every morning after getting their coffee to see where they are."

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The ESD Alliance Goes to DAC

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By Bob Smith, EDACafe

Jim Hogan, who regularly serves as a moderator for Alliance panels, moderated a Pavilion panel on AI and convolution neural networks. One panelist was Raik Brinkmann of ESD Alliance member company OneSpin.

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Formal Verification Has It Covered!

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By Dave Kelf, EE Times

Formal verification is a valuable verification tool for any hardware application, though its ability to debug automotive and mission-critical applications may prove to be its most effective use to date. As complexity grows and engineers analyze the behavior of their designs under a wider range of workloads, including malicious inputs, formal verification is employed to develop safety-critical hardware and an increasingly wide range of tasks. It ensures that suppliers of mission-critical applications, especially automotive electronics, meet rigorous ISO 26262 and other international safety critical standards that govern the development of safety-related electrical and/or electronic systems within road vehicles.

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Is The IP Industry Healthy?

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By Brian Bailey, Semiconductor Engineering

There are several reasons why companies buy IP. “There are some devices, such as memories, where it makes sense to obtain them from a company that will make sure they can be fabricated,” explains Dave Kelf, vice president of marketing for OneSpin Solutions. “It just isn’t worthwhile developing them because of the cost. Moving up a level, do we build a team to do the standard interfaces or is there a consultant who is an expert in the standard who can sell that IP? If it is not our core competency then it is probably not worth developing it. Finally, there are pieces such as processors, which require a lot of stuff in addition to the hardware, such as compilers. Do you want to get involved with that?”

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