The Increasingly Ordinary Task Of Verifying RISC-V
By Ann Steffora Mutschler, Semiconductor Engineering
Integrating an open-source core into a complex SoC is looking very familiar.
As RISC-V processor development matures and its usage in SoCs and microcontrollers grows, engineering teams are starting to look beyond the challenges of the processor core itself.
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At the same time, there are ever more choices for open-source RISC-V development boards and FPGA implementations, observed Salaheddin Hetalani, field application engineer at OneSpin Solutions. “These are great for software development and performance testing of target applications, and lower the cost to develop an idea into a prototype. But they are not a substitute for rigorous functional verification of the core, particularly when the core is extended with custom instructions. A formal verification app specific for RISC-V enables a quick and affordable core verification, delivering a level of quality that would normally be available only to IP providers with deep pockets and decades of experience. This is crucial in the development phase, to avoid wasting time debugging functional issues in the lab, or blowing a project delivering low quality hardware.”
