close By using this website, you agree to the use of cookies. Detailed information on the use of cookies on this website can be obtained on OneSpin's Privacy Policy. At this point you may also object to the use of cookies and adjust the browser settings accordingly.

RISC-V Meetups: In-Person Learning About the RISC-V Ecosystem

By Ted Marena, ElectronicDesign.com

Interested in knowing more about RISC-V, the fast-growing open ISA specification? One way is to attend a local meetup.

Electronic Design logo

[…]

OneSpin Solutions

The next presentation was from OneSpin Solutions. This company provides formal-verification tools for RISC-V Cores. What was memorable from this presentation were the bugs that their tools found in some open-source RISC-V cores. It was explained that RISC-V cores are challenging to verify because there are many optional instructions; complex micro-architectures are permitted, not to mention custom instructions.

The OneSpin Formal Verification tool provides complete coverage and guarantees full compliance to the RISC-V ISA and privileged ISA. OneSpin ran the open-source cores RI5CY and Rocket through its tool. Both designs had more than five issues, which were reported to the developers.

Back

Related Links