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Renesas' Toru Shimizu At DAC 2013

Abstract

  • Due to the wide range of different MCU types that are developed within a series of Renesas MCU’s in order to satisfy different applications we have developed the MCU-PF platform for both design and verification of a complete series of MCUs. A key issue is the effective verification for a combination of multiple IP components -this presents a significant task.
  • The test-case based simulation method of verification is widely used, but testcases are not reusable among MCU designs, and modification of the test-cases and the testbench takes a long time. Verification coverage is only partial when using test-case based simulation. As such we have developed the capability to use a Formal method of verification that provides full coverage of combinations of assertions while delivering significant reductions in both testing and verification time. Additional efficiency has been gained because the IP-Assertions are fully reusable along with the IP itself. This paper explains the methodology, its advantages and performance results compared to the simulation verification method.

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