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In the news

From Semiconductor Engineering: Graphing Toward Standardization

Even UVM doesn’t have universal buy-in. Dave Kelf, vice president of marketing for OneSpin Solutions, is not sure we have a firm footing with UVM. “It seems that SystemVerilog coupled with UVM, while considered the right direction for simulation-based flows, is simply too complex for engineers to get their heads around. No doubt a lot of this was due to its origins with multiple large companies pushing their own ideas and, possibly, over enthusiastic committee members with strong opinions not shared by others.”

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From Semiconductor Engineering: Formal Is Set To Overtake Simulation

Semiconductor Engineering sat down with a panel of experts to find out what caused this change and what more we can expect from formal verification technologies in the future. Participating in the panel were Pete Hardee, director of product management for Incisive Formal at Cadence; Oz Levia, vice president of marketing and business development at Jasper Design Automation; Pranav Ashar, CTO at Real Intent; Dave Kelf, marketing director at OneSpin Solutions; and Vigyan Singhal, CEO of Oski Technology.

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From EE Journal: A New Coverage Concept

The new Quantify product examines the completeness of the assertions and checkers in the design. The assertions are designed to catch problems during formal verification, but it’s possible to write ineffective assertions. Looked at another way, if assertions are poor or incomplete, then there may be code failures that could never be observed by the assertions.

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Electronic Design: Interview: Dr. Raik Brinkmann Comments On EDA Verification Trends

In the interview Dr. Raik Brinkmann, a co-founder of OneSpin Solutions, was asked about what he thinks about the current state of affairs is in the verification space as well as what trends he sees.

For example, Dr. Raik Brinkmann is considering: "As ever, verification continues to rapidly evolve. Coverage analysis (checking that the design has been fully tested or “covered”) is becoming more and more important as we move toward environments where coverage will drive the verification process. Formal verification is being leveraged more and more, both directly in flows and indirectly as part of other tools and solutions."

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Semiconductor engineering: The Road Ahead For 2014

Identifying market trends is the first step in being able to ensure you have the right products when people need them, so what will you need for 2014?

Semiconductor Engineering asked several thought leaders in the industry about the market drivers that are affecting their product planning operations for 2014. While almost everyone sees mobile devices continuing to be the major driver during 2014, there are some emerging areas that may start to have a larger impact.

„Automotive could create a convergence, explains Dr. Raik Brinkmann, president and CEO of OneSpin Solutions, „between powerful multimedia/communications platforms and safety-critical devices that could impact design and verification flows.

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EDA Cafe: Formal Verification’s Perfect Storm of Change

Another major player in the formal world,OneSpin Solutions, also some strong opinions to share. Please join us in welcoming OneSpin’s Director of Marketing Dave Kelf with his guest post: "In my opinion, not only will formal dominate verification, but my belief is that the effect of this technology will be as transformational as the advent of logic synthesis."

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Tech Design Forum: Formal verification enables Agile RTL development

Agile flow for verification

Agile development started in the software domain but the methodology shows promise for SoC verification. Formal verification techniques can help implement an Agile flow. Sergio Marchese describes how to implement Agile principles into hardware design in an article on Tech Design Forum.

The aim of this article is to share two experiences where a novel approach was used to develop register transfer level (RTL) modules. System Verilog Assertions (SVAs) were developed in parallel with RTL code using OneSpin Solutions’360-DV (Design Verification).

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