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In this three-part series, I look at broad challenges facing semiconductor verification and explain how they have grown to leave us facing a crisis of confidence. I will explore some of the key reasons why, despite astronomical growth in constrained random, emulation, and FPGA prototyping, we continuously grapple with poor quality.
This crisis of confidence has reached fever pitch: verification schedules routinely run late, bugs are often missed, silicon re-spins happen, and even worse, disgruntled customers are walking away from projects, hanging silicon vendors out to dry! When did this start? How did we get ourselves into such a mess? And how do we get out of it?
System complexity is skyrocketing, but tool support to handle concurrency and synchronization of heterogeneous systems remains limited.
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At the chip level, specific problem can be defined. “At an abstract level most of the problems are scheduling and arbitration problems,” says Ashish Darbari, director of product management for OneSpin Solutions. “I would go a step further and say that most are specific problems related to maintaining ordering in systems designed to work out-of-order. Ensuring that loads and stores remain ordered with respect to each master when accessing a shared memory to keep individual caches coherent is a different verification challenge. If not done correctly, it can cause memory sub-systems to lock up.”
Every so often, I undertake a project that reminds me why I love working in semiconductor marketing. Back in August, I hopped behind the wheel of a Tesla Model X to film a video for OneSpin about how formal verification can help designers to satisfy the ISO 26262 automotive safety standard. If you haven’t yet seen the video, you can watch it here: bit.ly/2ycK5Yp
OneSpin had a cool, laid back, coffee shop-like environment right next to the DAC pavilion this year. OneSpin formal tools this year focused on ISO 26262 and Safety Critical design, with some new apps that target fault verification and diagnostic coverage.
Custom hardware also provides other benefits. “Emulators, particularly those based on custom chips, have a number of advantages,” says Dave Kelf, vice president of marketing for OneSpin Solutions. “They tend to offer faster compile times and therefore a tighter debug turnaround loop, they have greater visibility into the design, and have better connections with simulation and the EDA flow.”
Raik Brinkmann, president and CEO of OneSpin Solutions, sat down to talk about artificial intelligence, machine learning, and neuromorphic chips. What follows are excerpts of that conversation.
When is a design ready to be taped out? That has been one of the toughest questions to confront every design team, and it’s the one verification engineers lose sleep over.
Exhaustive coverage has not been possible since the 1980s. Several metrics and methodologies have been defined to help answer the question and to raise confidence that important aspects of a block have been verified. But those metrics and methodologies have struggled to keep up with growing complexity, and they do not scale to the system level. A new framework for understanding coverage and completeness is required.
DVCon Europe is on the horizon, and this year’s program should prove to be very timely. Chips and systems are getting more complex, verification is becoming more difficult, and formal has emerged as a critical piece of the verification suite
The lineup this year tackles some key issues facing a changing semiconductor landscape. During a Monday tutorial, “Next Generation ISO 26262-based Design Reliability Flows,” Jörg Grosse, product manager functional safety, and Sanjay Pillay, Austemper Design Systems’ CEO, will demonstrate a complete safety development process.