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In the news

Intellectual Property: Trust… But Verify

By John Hallman, Product Manager Trust & Security, OneSpin | Blog for Semiconductor Engineering

As the supply chain of components and IP expands, so too do the opportunities for adversarial tampering.

For those around the microelectronic component industry for many years, we have seen quite a transformation of capability, sourcing of the supply chain, and now threats to these devices that drive the technology in our world today.

These integrated circuits (ICs), once so simple as a few transistors, have continued to follow Moore’s Law and are now made up of tens of billions of transistors. ICs have become so complex that they too are now made up of many independent modules, often referred to as third-party intellectual property (3PIP).

In addition to the increased capability, the source of the components, as well as the 3PIP, has become a global effort. Examples of this globalization are evident by design and production of such major systems as the Apple iPhone and the F-35 fighter jet. The major suppliers for the Apple iPhone all demonstrate a global contribution to a complex supply chain. Similarly, several countries, including the U.S., Netherlands, Norway, Canada, Australia, United Kingdom, Turkey, and Italy, are all source supply for the F-35.

As the complexity of the system, components, and the supply chain all increase, the opportunity for adversarial tampering causes a growing concern.

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How To Integrate An Embedded FPGA

By Brian Bailey, Semiconductor Engineering | Feat. Tobias Welp, Engineering Manager, OneSpin

Adding an eFPGA into an SoC is more complex than just adding an accelerator.

Choosing to add programmable logic into an SoC with an eFPGA is just the beginning. Other choices follow involving how many lookup tables (LUTs), how much routing and what topology, how will data be transferred in and out of the fabric, does data need to be coherent with system memory, how will it be programmed and tested, and what RTL functions need to be embedded into the programmable fabric itself?

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Formal verification can help. “The FPGA fabric must be verified twice, first by the vendor and then by the user programming it,” explains Tobias Welp, engineering manager for OneSpin Solutions. “Formal equivalence checking, a key verification step, is even more important when fabric is involved because FPGA synthesis tools offer advanced optimizations to meet power, performance, and area (PPA) goals. Some of these optimizations change the state space of the design and move logic across register boundaries, so sequential equivalence checking is required. This should be performed in multiple stages to ensure that the input RTL, the post-synthesis netlist, the placed-and-routed netlist, and the programming bitstream are all functionally equivalent.”

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Why IP Quality is So Difficult to Determine

By Ann Steffora Mutschler, Semiconductor Engineering | Feat. Tom Anderson, Technical Marketing Consultant, OneSpin

How it is characterized, verified and used can have a big impact on reliability and compatibility in a design.

Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends up on how and where it is used and in part because even the best IP may work better in one system than another—even in chips developed by the same vendor.

This has been one of the challenges with IP over the years. In many cases, IP is poorly characterized, regardless of whether that IP was commercially or internally developed by a chipmaker. But as chips become more complex, subject to more interactions from multiple power domains and use cases, even the best intentions to characterize IP can go awry.

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Just the term “quality” is overloaded due to associations with “Six Sigma” and other specific industry initiatives, suggested Tom Anderson, technical marketing consultant at OneSpin Solutions. “The term ‘IP integrity’ is broader in scope.”

Assuring the integrity of a design encompasses four critical dimensions—functional correctness, safety, security and trust. Functional correctness is the focus of traditional verification, ensuring that the design meets its functional specification. In the case of IP, this specification often involves a standard such as the USB 3.0 interface or the RISC-V instruction set architecture (ISA).

But functional correctness alone isn’t sufficient for many designs. “Safety-critical applications, such as mil-aero, embedded medical devices and self-driving cars, require that designs operate correctly in the field,” said Anderson. “Random errors such as alpha particle hits must not compromise design safety. Many types of IP are used for these applications, so the providers must account for safety, and the IP integrators must confirm this. In many of these same applications, the IP must not contain security vulnerabilities that could allow malicious actors to take control of chips containing the IP in the field. Both IP providers and IP integrators must screen designs for any accidental security holes.”

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DAC 2019 Preview: OneSpin Solutions

By TDF Editor, Tech Design Forum

OneSpin Solutions' recent launches for Intel FPGAs and RISC-V ISA compliance will be at the forefront of its exhibition presence at the Design Automation Conference next month (read more about them here). The company will also be active in DAC’s Designer Track.

DAC 2019 is to take place at the Las Vegas Convention Center from June 2-6. The exhibition runs June 3-5 and OneSpin will be present at Booth #308.

In addition to demonstrations (which can be booked here), staff will be on hand to discuss recent technical papers and research from the company.

Nicolae Tusinschi, product specialist, design verification , will present, “Unbounded Formal Verification of RISC-V CSRs with Interval Property Checking,” during the Designer Track session on “New Frontiers in Formal and Static Verification” (Monday June 3, 10:30am-12:00pm, Room N262).

During the Designer/IP Track Poster Networking Reception, Sasa Stamenkovic, senior field application engineering, will be available to discuss “Advances in Formal Connectivity Checking –– A Case Study on a Multi-Billion-Gate SoC” (Monday June 3, from 5:00pm).

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Week In Review: Design, Low Power

By Jesse Allen, Semiconductor Engineering

OneSpin Solutions unveiled a formal RISC-V Verification App. The App is intended to exhaustively verify that RSIC-V cores are developed and integrated with zero bug escapes and guarantee full compliance with the ISA, even with the range of configuration options available. OneSpin says the automated solution needs only a few days to set up and only two hours to run on a complete core. In addition, OneSpin’s 360 EC-FPGA now supports three Intel FPGA families, Stratix 10, Arria 10, and Cyclone V using Intel Quartus software for synthesis and place-and-route. The company says the move to support FPGAs used in high-bandwidth applications meets demand from verification engineers for formal equivalence checking solutions that ensure functional correctness of FPGA designs. The tool is implemented in the FPGA flow from RTL to place-and-route to check RTL code against a post-synthesis, gate-level netlist.

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OneSpin Adds SEC for Intel FPGAs and App for RISC-V ISA Compliance

By TDF Editorial Staff, Tech Design Forum

OneSpin Solutions has extended its EC-FPGA automated sequential equivalence checking software to cover three of Intel’s field programmable gate array (FPGA) lines: Stratix 10, Arria 10 and Cyclone V.

The company has also launched an app for use inside its RISC-V Integrity Verification Solution aimed at safety- and security-critical applications and specifically targeting the increasingly popular open-source core.

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Evolution of Verification Engineers (Experts at the Table, Part 3)

By Brian Bailey, Semiconductor Engineering | Feat. Tom Anderson, Technical Marketing Consultant, and Jim Hogan, Board Director, OneSpin

The role of a verification engineer will change and start to look a lot like knowledge management.

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief executive office for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions architect for Cadence Design Systems; and Tom Anderson, technical marketing consultant for OneSpin Solutions. What follows are excerpts of that conversation.

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Anderson: We are dancing around the idea of correct by construction. It has been around forever. Would you want a model that you don’t have to verify? That is the goal of correct by construction. You have a model that is correct, maybe through exploration, maybe through other techniques that you used to validate and verify what you are worried about. But it is a single model, and from that you generate the design. Maybe we are getting to the point where the top level of an SoC, defined to be correct by construction, may actually work.

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Incremental System Verification (Experts at the Table, Part 2)

By Brian Bailey, Semiconductor Engineering | Feat. Tom Anderson, Technical Marketing Consultant, OneSpin; and Jim Hogan, Board Director, OneSpin

How does a PSS model get verified and who will create that model? What happens when models extend beyond the specification?

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief executive office for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions architect for Cadence Design Systems; and Tom Anderson, technical marketing consultant for OneSpin Solutions. What follows are excerpts of that conversation.

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Anderson: This is certainly an example of the way in which verification will influence design. You are playing with a level of parameters that affect what the hardware does. This is another dimension of the general problem.

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