The RISC-V Foundation, in collaboration with the Linux Foundation, is hosting free, half-day “Getting Started with RISC-V” events in Tel Aviv, Munich, Berlin, Tallinn, Paris and London from Sept. 16-26. RISC-V Foundation members will give presentations and live demonstrations showcasing innovation RISC-V solutions and implementations. Register today to save your spot!
OneSpin Solutions is one of the featured RISC-V Foundation members in the EMEA roadshow, presenting the session, “Verifying the Full Scope of RISC-V Integrity.” OneSpin offers a range of EDA solutions for digital integrated circuits, which enables users to address design challenges in areas where reliability really counts: safety-critical verification, SystemC/C++ high-level synthesis (HLS) code analysis and FPGA equivalence checking. Read on to learn more about the company and what it will be showcasing at the events.
By Nicolae Tusinschi, Product Specialist Design Verification, OneSpin
Last month, we discussed the growth of the RISC-V open processor ecosystem, the two main organizations driving it, and the role that OneSpin plays. In addition, we have become very active in the RISC-V community and have more than a dozen technical articles published, conference talks presented, and upcoming talks accepted. We tend to focus on the challenges of verifying RISC-V IP cores and system-on-chip (SoC) designs containing these cores. Since I have been on the front line speaking at many of these conferences, I’d like to share my perspective on how the industry’s view of RISC-V verification is growing and evolving.
By Ann Steffora Mutschler, Semiconductor Engineering | Featuring Raik Brinkmann, President and CEO of OneSpin
‘Digital Twins’ are one of the new, fashionable key concepts for system developers, but do they fit with EDA? How many different types of engines do these twins run on – abstract simulation, signal-based RTL simulation, emulation, prototyping, actual silicon? What should the use models be called for digital twinning – like reproduction of bugs from silicon in emulation? Or optimizing the implementation usage using data run safely in virtual and FPGA based prototyping?
By Amelia Dalton, EE Journal | Feat. Rob van Blommestein, Head of Marketing, OneSpin
In this week’s episode of Fish Fry, we are swimming in SoCs! Randy Fish (UltraSoC) joins us to discuss the deep waters of embedded analytics and AI platform debug. Ramsay Allen (Moortec) and I chat about the rising tide of advanced chip node designs and the benefits of in-chip monitoring IP. Finally, Rob van Blommestein (OneSpin) and sail through the choppy waters of IC verification.
By Ann Steffora Mutschler, Semiconductor Engineering | Feat. Tom Anderson, Technical Marketing, OneSpin
Semiconductor Engineering sat down to discuss partitioning with Raymond Nijssen, vice president of system engineering at Achronix; Andy Ladd, CEO at Baum; Dave Kelf, chief marketing officer at Breker; Rod Metcalfe, product management group director in the Digital & Signoff Group at Cadence; Mark Olen, product marketing group manager at Mentor, a Siemens Business; Tom Anderson, technical marketing consultant at OneSpin; and Drew Wingard, CTO at Sonics [Sonics was acquired by Facebook in March 2019]. What follows are excerpts of that discussion.
By Brian Bailey, Semiconductor Engineering | Feat. Dominik Strasser, VP Engineering, OneSpin
Semiconductor Engineering sat down to discuss debugging complex SoCs with Randy Fish, vice president of strategic accounts and partnerships for UltraSoC; Larry Melling, product management director for Cadence; Mark Olen, senior product marketing manager for Mentor, a Siemens Business; and Dominik Strasser, vice president of engineering for OneSpin Solutions.