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By Sven Beyer and Sergio Marchese, OneSpin Solutions
SystemVerilog assertions can nicely capture many hardware requirements. However, more is needed for security verification.
Safety- and security-critical systems, such as connected autonomous vehicles, require high-integrity integrated circuits (ICs). Functional correctness and safety are necessary to establish IC integrity, but not sufficient. Security is another critical pillar of IC integrity. Systems and products using ICs with security vulnerabilities ultimately undermine the safety and privacy of people. However, hardware security is still in its infancy.
By Tom Anderson, Technical Marketing Consultant, OneSpin Solutions
Automatisierte Konnektivitatsprufung. Die Verbindungen zwischen den Designblocken und I/O-Zellen komplexer Chips lassen sich nicht mittels Inspektion verifizieren. Simulation und Emulation konnen zwar Bugs aufspuren, bleiben aber unvolistandig. Formale Tools dagegen finden nicht nur alle Fehler – sie konnen das auch beweisen.
By Brian Bailey, Semiconductor Engineering | Featuring Rob van Blommestein, Head of Marketing at OneSpin
Can a software engineer create hardware? It may be possible, but not in the way that existing high-level synthesis tools do it.
The ability to automatically generate optimized hardware from software was one of the primary tenets of system-level design automation that was never fully achieved. The question now is whether that will ever happen, and whether it is just a matter of having the right technology or motivation to make it possible.
By Ann Steffora Mutschler, Semiconductor Engineering | Featuring Nicolae Tusinschi, product specialist design verification for OneSpin
The definition has changed, and so has the impact on the design process.
Spurred by the latest cyclical development boom, the semiconductor industry is entering a new golden era of custom processors, but this time ‘custom processor’ means something different.
The RISC-V Foundation, in collaboration with the Linux Foundation, is hosting free, half-day “Getting Started with RISC-V” events in Tel Aviv, Munich, Berlin, Tallinn, Paris and London from Sept. 16-26. RISC-V Foundation members will give presentations and live demonstrations showcasing innovation RISC-V solutions and implementations. Register today to save your spot!
OneSpin Solutions is one of the featured RISC-V Foundation members in the EMEA roadshow, presenting the session, “Verifying the Full Scope of RISC-V Integrity.” OneSpin offers a range of EDA solutions for digital integrated circuits, which enables users to address design challenges in areas where reliability really counts: safety-critical verification, SystemC/C++ high-level synthesis (HLS) code analysis and FPGA equivalence checking. Read on to learn more about the company and what it will be showcasing at the events.
By Nicolae Tusinschi, Product Specialist Design Verification, OneSpin
Last month, we discussed the growth of the RISC-V open processor ecosystem, the two main organizations driving it, and the role that OneSpin plays. In addition, we have become very active in the RISC-V community and have more than a dozen technical articles published, conference talks presented, and upcoming talks accepted. We tend to focus on the challenges of verifying RISC-V IP cores and system-on-chip (SoC) designs containing these cores. Since I have been on the front line speaking at many of these conferences, I’d like to share my perspective on how the industry’s view of RISC-V verification is growing and evolving.
By Ann Steffora Mutschler, Semiconductor Engineering | Featuring Raik Brinkmann, President and CEO of OneSpin
‘Digital Twins’ are one of the new, fashionable key concepts for system developers, but do they fit with EDA? How many different types of engines do these twins run on – abstract simulation, signal-based RTL simulation, emulation, prototyping, actual silicon? What should the use models be called for digital twinning – like reproduction of bugs from silicon in emulation? Or optimizing the implementation usage using data run safely in virtual and FPGA based prototyping?
