Formal verification traditionally has been regarded as an advanced technique for experts to thoroughly verify indi- vidual blocks of logic, or perhaps small clusters of blocks. The appeal of formal techniques is the exhaustive analysis of all possible behavior for the design being verified. This stands in sharp contrast to simulation, which exercises only a tiny fraction of possible behavior by running specific tests. If no test triggers a design bug, the bug will not be found. If the bug is triggered but no change in results is observed, the bug will not be found. Given a sufficiently robust set of properties to describe intended behavior, formal tools can not only find all bugs but also prove that there are no more bugs to be found.
By Ann Steffora Mutschler, Semiconductor Engineering | Feat. Sasa Stamenkovic, senior field applications engineer, OneSpin Solutions
In the past, FPGAs were considered a relatively quick and simple way to get to market before committing to the cost and time of developing an ASIC. But today, both FPGAs and eFPGAs are being used in the most demanding applications, including cloud computing, AI, machine learning, and deep learning. In some cases, they are being combined with an ASIC or some other type of application-specific processor or accelerator inside a chip, a package or a system. As a result, requirements for effective power, performance, and area (PPA) are every bit as strict as for ASICs and full-custom chips, and the tradeoffs are equally complicated and often intertwined.
By Sven Beyer and Sergio Marchese, OneSpin Solutions
SystemVerilog assertions can nicely capture many hardware requirements. However, more is needed for security verification.
Safety- and security-critical systems, such as connected autonomous vehicles, require high-integrity integrated circuits (ICs). Functional correctness and safety are necessary to establish IC integrity, but not sufficient. Security is another critical pillar of IC integrity. Systems and products using ICs with security vulnerabilities ultimately undermine the safety and privacy of people. However, hardware security is still in its infancy.
By Tom Anderson, Technical Marketing Consultant, OneSpin Solutions
Automatisierte Konnektivitatsprufung. Die Verbindungen zwischen den Designblocken und I/O-Zellen komplexer Chips lassen sich nicht mittels Inspektion verifizieren. Simulation und Emulation konnen zwar Bugs aufspuren, bleiben aber unvolistandig. Formale Tools dagegen finden nicht nur alle Fehler – sie konnen das auch beweisen.
By Brian Bailey, Semiconductor Engineering | Featuring Rob van Blommestein, Head of Marketing at OneSpin
Can a software engineer create hardware? It may be possible, but not in the way that existing high-level synthesis tools do it.
The ability to automatically generate optimized hardware from software was one of the primary tenets of system-level design automation that was never fully achieved. The question now is whether that will ever happen, and whether it is just a matter of having the right technology or motivation to make it possible.