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SystemC Evolution Day

October 28, 2021 | Virtual Event

Product Specialist Vlada Kalinic of OneSpin: A Siemens Business will present “Achieving IC Integrity for SystemC Designs.” (Time TBA.)


High-level synthesis (HLS) transforms algorithmic and potentially untimed design models, often written in SystemC and C++, to fully timed RTL design blocks. HLS tools are particularly popular as a method to rapidly generate design components with varying microarchitectures, while optimizing algorithm processing datapaths rapidly and effectively. This provides substantial benefits in terms of flexibility and time-to-market. Consequently, HLS is now in use at many large semiconductor and electronic systems companies. However, the verification options for SystemC and C++ designs have not kept pace with the synthesis technology.
Due to the limited availability of SystemC tools, much of the verification task is performed on the resulting synthesized RTL code, introducing a level of indirection that makes correcting issues at the SystemC/C++ level complex and time consuming. In addition, artifacts of the SystemC standard, including the lack of an unknown, or X, state and potential race conditions between threads, result in further ambiguity that must be eliminated before synthesis. Specific issues related to this abstract design level may be easily tackled with the right verification methods, improving final design quality.
Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. A broad range of formal verification techniques can be applied to SystemC and C++ components with varying levels of timing and code abstraction. In this tutorial, we’ll explore how these formal techniques and provide real-world examples of how the technology was applied to achieve success.


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