RISC-V SUMMIT 2019
San Jose, California, USA | December 10-12, 2019
Join us for this year's RISC-V Summit and learn about the disruptive force driving the next generation of hardware, software, and IP. OneSpin will be represented with a dedicated booth, and our product specialist design verification, Nicolae Tusinschi, will give a presentation on verifying RISC-V SoCs.
WEDNESDAY December 11, 11:30 AM - 12:30 PM
Pre-Silicon Detection of Hardware Trojans and security vulnerabilities in RISC-V Cores
Sven Beyer, Product Manager Design Verification, will present a poster entitled “Pre-Silicon Detection of Hardware Trojans and security vulnerabilities in RISC-V Cores,” co-authored by Blake Buschur of Edaptive, on Wednesday, Dec. 11 from 11:30 AM to 12:30 PM in the poster gallery on the exhibit floor.
WEDNESDAY December 11, 2:50 PM - 3:10 PM
More than the Core: Verifying RISC-V SoCs
Verifying RISC-V designs is critical for technical and commercial success. Compliance to the standard specifications and complete interoperability are essential to complete with older processor families with decades of proven silicon. RISC-V processor designers, whether in-house or core providers, must apply the most rigorous verification methodologies and document this process to build the confidence of potential integrators.
Successful RISC-V verification extends beyond the core itself. This talk focuses on the needs of engineers integrating one or more RISC-V processors into a system-on-chip (SoC) design. The SoC team faces four major verification challenges. The first is re-running some or all of the verification performed on the standalone core as part of their acceptance criteria. This is much easier if the verification is performed using a third-party solution.
The flexibility of the RISC-V architecture and the many choices for the core integrator add to the verification complexity. It may be possible to configure the core within the range of optional functionality defined by the RISC-V Instruction Set Architecture (ISA). RISC-V is defined to accommodate a wide range of microarchitectural implementations, and these must also be verified.
Further, the ISA specifications permit extensions, such as addition of custom instructions, which must be verified to ensure that the new functionality works and that none of the baseline functionality is broken. Complete core verification goes well beyond compliance to the baseline ISA, covering architectural options, microarchitecture, and extensions. This task is the second major verification challenge for SoC teams.
Many RISC-V applications have security and trust requirements, so integrators need to check that no design errors offer vulnerabilities for adversary attack and that no hardware Trojans have been deliberately inserted. Many of the security and trust checks should be run on the rest of the SoC and not just on the core. In addition, for safety-critical applications, safety verification must be performed at the full-chip level of the SoC.
Safety, trust, and security verification is the third major challenge faced by teams integrating a RISC-V core into their SoC. The final challenge is verifying that the core has been properly integrated into the complete chip. This involves using formal connectivity checking to ensure that all signals are hooked up correctly. In fact, all four challenges can be addressed by a verification methodology based largely on formal technology.
This talk presents an available solution that addresses all four verification challenges for SoC teams adopting RISC-V. It presents examples of issues found using this approach on actual chip designs, including PULPino, available in open-source repositories. It is appropriate, and highly recommended, for managers, designers, and verification engineers developing or integrating RISC-V processor cores.