December 14-16, 2021| Virtual Event
OneSpin: A Siemens Business will host a short workshop at this year's DVCon India virtual event.
Verification of RISC-V Cores
Pre-silicon verification of processors is a challenging, time-consuming task. IP providers offering proprietary ISA cores leverage decades of effort and state-of-the-art EDA tools. RISC-V cores for commercial applications must achieve the same level of quality while facing the additional challenge of their own custom instructions of registers.
This session presents a fully-fledged environment for the formal verification signoff of RISC-V cores. Its main inputs are the target RTL core and a description of the custom extensions. It produces a set of assertions capturing that the RTL faithfully implements the chosen ISA with its custom extensions and nothing else. These assertions are exhaustively proven on the RTL. The session continues showing how to deploy the environment on a concrete RTL design.
The environment has been used on numerous open-source cores successfully. The session concludes with a section sharing general information and bugs found in past and ongoing projects, including RocketChip, ibex, and CV32E40P.