close By using this website, you agree to the use of cookies. Detailed information on the use of cookies on this website can be obtained on OneSpin's Privacy Policy. At this point you may also object to the use of cookies and adjust the browser settings accordingly.

DVCon Europe 2021

October 26–27, 2021 | Virtual Event

Don’t miss Product Specialist Design Verification Nicolae Tusinschi’s tutorial, “Automated Code Checks To Accelerate Top-Level Design Verification,” which airs October 16 from 16:00–17:00 CET on Stream 3 of the virtual conference. 


Integrated circuit designers are under constant pressure to deliver bug free code that meets evermore rigorous requirements. It is well known that the more bugs that can be detected early in the development process, the faster and easier that development effort will be. However, early bug detection requires a verification overhead on the designer that can be onerous and impact the design process.

The two major methods that designers can leverage to detect bugs are static linting and simulation. Linting requires low set up and can detect a class of bugs based on the syntax of the code, although does tend to report many potential issues that have to be analyzed and is limited when examining the sequential operation of a block. Simulation is focused on the code operation but requires a greater degree of set up, in the form of directed stimulus creation, which are usually not available at this stage in the process and will only detect issues in scenarios that the provided stimulus is examining.

What designers require for early and automated detection of implementation issues are fast and easy ways to set up static checks for the sequential operation of the code in an exhaustive fashion, without relying on user provided stimulus. Automated formal code inspection helps to rapidly eliminate errors in a piece of RTL, prior to functional verification and synthesis, while providing a fully automated, and simple use-model. Three different verification perspectives are achieved.

  • Structural Analysis: Focused syntactic and semantic analysis of source code.
  • Safety Checks: Exhaustively verify the absence of common sequential design operation issues and failure debugging.
  • Activation Checks: Ensures that specific design functions can be executed and are not blocked by unreachability.

Each of these pieces of technology are fully automatic and require no assertions to be created by the user. There is no need to write stimulus, create assertions or understand the formal mechanisms being employed.

This tutorial will dive into how this technique can be applied. We’ll explore real-world case studies that prove the effectiveness of this technology.


Conference attendees are encouraged to visit the Siemens EDA virtual booth to meet our verification experts and learn about the OneSpin 360™ suite of IC integrity solutions.


Related Links