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Design & Reuse IP-SoC Days

Grenoble, France | December 3–4, 2019

Design & Reuse IP-SoC Days logo

OneSpin’s Mark Hampton joins representatives from Intel, SiFive, and Synopsys to discuss the growing importance of security in the hardware development lifecycle.


WEDNESDAY December 4th, 10:00–11:00 AM

Is the New Emerging Standard IP Security Assurance (IPSA from Accellera Working Group) the Solution?

In recent years, many hardware security weaknesses arising from integrated circuit hardware vulnerabilities have been exposed. These include lack of virtual machine isolation, secure credential leaks, and privilege escalation. These have put hardware design in the spotlight and raised questions about IC security.

  • How is security addressed over the hardware development lifecycle today?
  • How should we assess and mitigate security risk in IC design going forward?
  • Do we have adequate methodologies, procedures and technology to address it?

Moreover, today’s SoCs and ASICs are not monolithic devices coming from a single source, but rather are composed as a collection of various components, often including 3rd party IPs.

  • Does this raise further or different concerns about the management of security risk?
  • How much risk does the silicon owner (integrator) inherit?
  • What mitigations should be implemented in the IP, and by whom?
  • And what residual security concerns exist that should be addressed by the integrator?

Answering these questions should be crucial to all SoC/ASIC integrators, even if their approaches are different. Can an emerging Accellera IP Security Assurance (IPSA) standard provide the solution? Do we even need a new standard here?

Panelists:

Mark Hampton, Safety & Security Consultant, OneSpin Solutions
Ireneusz Sobański
, Senior Validation Engineer, Intel
Yann Loisel, Security Architect, SiFive
Chris Dunn, Staff R&D Engineer, Synopsys

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