Osmosis for DoD | October 13–14, 2020 | Virtual Event
Join OneSpin for a Special Department of Defense Users' Group Event
What is Osmosis?
Osmosis stands for OneSpin Meeting on Solutions, Innovation, & Strategy. It is a users’ group for customers and partners of OneSpin Solutions, provider of electronic design automation (EDA) tools for integrated circuit (IC) integrity verification. Osmosis signifies balance and two-way movement—in this case, of technical knowledge and expertise among OneSpin's experts and users. If IC integrity is important to you—particularly in the areas of functional correctness, safety, security, or trust—then this event is for you!
Osmosis for DoD is a two-day virtual event for current and prospective users of OneSpin 360™ verification solutions within the Trusted Silicon Stratus (TSS) environment and across the broader Department of Defense community.
Day 1 At-A-Glance: OneSpin Users Showcase
Tuesday, October 13, 2020 | 10:00 AM EDT
Opening Remarks: Len Orlando, Air Force Research Laboratory (AFRL)
Keynote Address: Matthew Casto, Office of the Secretary of Defense
User Case Studies:
- Aerospace Corporation
- Air Force Research Laboratory (AFRL)
- Battelle Memorial Institute
- Edaptive Computing
- Sandia National Laboratories
Day 2 At-A-Glance: OneSpin Experts All-Access
Wednesday, October 14, 2020 | 10:00 AM EDT
Keynote Address: Raik Brinkmann, President & CEO, OneSpin
Technical Deep Dives:
- Functional Correctness
- Trust & Assurance
- FPGA/FPGA Retargeting
- Certification Training for Formal Verification Methodologies
Breakout Sessions with OneSpin's Experts:
- The Ins and Outs of Trust & Assurance
- RISC-V and the Open Source Movement
- Safety and Standards in Mil/Aero: What's Next for Hardware Safety Compliance?
Read on for complete event details and to register!
Full Agenda for Osmosis for DoD
Click to expand each day's agenda detailsAll times are shown in Eastern Daylight Time (EDT) and are subject to change
10:00 Welcome to Osmosis for DoD, Day 1
OneSpin Master of Ceremonies
10:05 Opening Remarks to the TSS and DoD Communities
Len Orlando, Air Force Research Laboratory (AFRL)
10:20 Keynote Address
Matthew Casto, Office of the Secretary of Defense
10:50 Q&A Session for Opening Speakers
11:00 Ensuring Completeness of Formal Verification with GapFree: To End or Not to End (Property Writing) | Sandia National Laboratories
Ratish Punnoose, Distinguished Member of Technical StaffA challenge with formal verification of RTL designs is knowing how much verification is enough. This is especially true when it comes to knowing when to stop writing additional properties. How can we achieve confidence that enough properties have been checked to verify the correctness of the design? OneSpin's GapFreeVerification methodology provides an answer to this problem. The methodology results in an automated check of the written properties to ensure that all design behaviors have been captured.
11:30 Evaluation of OneSpin Trust Assessment Platform for Hardware Trojan Detection | The Aerospace Corporation
Garrett Chan, Engineering Manager, and Vikram Rao, Sr. Engineering SpecialistOneSpin’s Trust Assessment Platform is being evaluated by the Aerospace Corporation to be used as part of our pre-silicon IV&V service for hardware Trojan detection. ASICs, FPGAs, and SoCs enable mission-critical functions across national security space (NSS) and terrestrial programs, but they may be vulnerable to anomalies such as hardware Trojans. This problem motivates the Zero-trust approach, which assumes that no microelectronics acquired are “safe”, and instead require verification, validation, and testing before use. To comply with the Zero-trust approach, the Aerospace Corporation provides a pre-silicon IV&V service to programs, as part of a larger ASIC/FPGA assurance framework. The pre-silicon IV&V service focuses on Trojan detection using commercial verification and emerging security tools. As part of the OneSpin Trust Assessment Platform evaluation, the Aerospace Corporation chose host designs representing real-world mil/aero IPs of varying size and complexity. Hardware Trojan triggers and payloads were developed (coded) based on the Aerospace Corporation’s hardware Trojan catalog and taxonomy, as well as academic literature, and then inserted into the host designs. “Golden” host designs (without Trojans inserted) served as a baseline, and versions of the Trojan designs were used to evaluate the effectiveness of the OneSpin Trust Assessment Platform in hardware Trojan detection.
12:00 Leveraging OneSpin for Automated Risk Assessment | Battelle Memorial Institute
Nick Darby, Data ScientistAutomated and replicable risk assessment strategies are essential to establishing trust as an equal to power, performance, and area in microelectronics design flows. Leveraging microelectronic design tools in the TSS environment, our team demonstrates a data-driven approach for automating risk assessment across varying design processes. To analyze our corpus of design flows, we automate the generation of analysis scripts, instrument tool output to extract quantitative indicators, and store the extracted values in relational data structures. Capturing both design flows and analysis results in relational structures facilitates analysis using powerful relational artificial intelligence (RAI) tools. These data structures also allow for naïve capture of alternative design flows, avoiding expertise-intensive localization and information loss during tabularization. OneSpin engineers are working with Battelle not only to apply their tools, but also to identify how the formal verification process can detect different threat models. The OneSpin tool suite is particularly well suited for automating risk assessment because it links a powerful formal verification engine with automated assertion generation tools. We also automate comparisons of pre- and post-synthesis RTL for formal logical equivalence testing, effectively validating unobserved synthesis results in a trusted computational environment.
12:30 Lunch Break
13:15 TSS SoC Sign-Off Methodology | Edaptive Computing
Christopher Diltz, Senior Verification EngineerIntegrated circuits have exploded in growth in their applications in transportation, security, and the Internet of Things (IoT). This growth has led to increasingly complex design implementations that require more thorough verification test runs. With smaller time-to-market requirements, verification engineers face a bottleneck in the time it takes to exhaustively verify and sign off on a design. As a result, verification engineers are looking for more efficient methodologies to reduce the time needed to check a design and meet production goals. This case study will highlight the application of OneSpin 360 EC (Equivalence Checking) to two iterations of a design test article. We will explore how it can be used to reduce runtime on other formal checks. Included in the discussion: design overview, methodology, our results, and next steps going forward.
13:45 Securing RISC-V Military Projects | Edaptive Computing on behalf of Air Force Research Laboratory (AFRL)
Paul McHale, Principal Verification EngineerThe use of the RISC-V open source instruction set architecture (ISA) has increased substantially over the last few years. This growth has led to myriad different RISC-V implementations in academia, industry, and defense that require thorough verification in order to ensure that the designs adhere to the correct ISA specifications. With the increasing complexity in RISC-V implementations and high learning curve to apply thorough verification to the designs, verification engineers are looking to apply robust and automated tools to close the gap and ensure complete coverage. In this case study, we discuss and highlight the rapidly evolving RISC-V verification landscape in military projects, the application of OneSpin’s Processor Integrity Solution to verify a design test article’s adherence to the RISC-V ISA, and the future of RISC-V in military applications.
14:15 Closing Remarks and Preview of Day 2
OneSpin Master of Ceremonies
10:00 Welcome to Osmosis for DoD, Day 2
OneSpin Master of Ceremonies
10:05 Keynote Address: IC Integrity in Today's Evolving World
Raik Brinkmann, President & CEO, OneSpinWhen we say "IC integrity," what do we mean? On the surface, we are addressing the functional correctness of a design, but there's much more to it than that: safety, security, and trust all come into play in myriad ways and can vary widely with the market vertical and end use of an ASIC, FPGA, or SoC. To open Day 2 of Osmosis for DoD, President and CEO Raik Brinkmann explores the far-reaching and nuanced ramifications of IC integrity—and the potentially dire consequences of a lack thereof—in today's increasingly connected, automated, electronically-dependent world. From this broader context, Raik will then draw back the curtain and offer Osmosis attendees privileged insights into OneSpin's vision, mission, and solution development roadmap.
10:30 OneSpin Technical Deep Dive: Functional Correctness from Start to Finish
Nicolae Tusinschi, Product Specialist Design VerificationThe early elimination of bugs in an IC development process saves time and energy. This places pressure on component designers to perform more verification. However, given traditional simulation-based verification techniques, the ultimate result of this trend is designers spending more time creating stimulus and getting involved with overall verification, and less on creative design. Automated design code verification and functional analysis using automated apps allows for rapid design iterations along with comprehensive assertion-based verification. Combining with unique model-based mutation coverage, OneSpin’s functional correctness solution is crucial in today’s large and complex SOCs—this session delves into the particulars and looks ahead to what comes next.
11:15 OneSpin Technical Deep Dive: Supporting DoD Trust and Assurance on the TSS
John Hallman, Product Manager Trust & SecurityAs part of the Trusted and Assured Microelectronics initiative, OneSpin verification tools are available for DoD use on the TSS. Technologies built upon world class formal engines provide a great foundation for advanced integrity solutions. New apps methods include an automated assessment platform, structural and intelligent pattern detection, and new research into FPGA and SOC hardware/software co-verification techniques. In this presentation, users will see existing OneSpin solutions available today that address DoD trust and assurance challenges and get a preview of new technologies needed to propel us forward in this rapid evolving field.
12:00 Lunch Break
12:45 OneSpin Technical Deep Dive: Achieving RISC-V Integrity
Sven Beyer, Chief ScientistRISC-V is one of the hottest trends in the industry these days, with core providers from textbook open source to high-end commercial ones. The freedom to configure the RISC-V ISA in detail to the system needs, including custom instructions, is one of its strong appeals. However, this freedom comes with an equally great responsibility to assure integrity of the implemented RISC-V core, from ISA compliance over absence of hidden instructions or registers to absence of side-channel types of attacks. In this technical deep dive, we will take a look at OneSpin's current RISC-V apps for architecture and verification. We will also share some insight into the trust, assurance, and security RISC-V extensions planned for the upcoming OneSpin 360 2021.1 release.
13:30 OneSpin Technical Deep Dive: Overcome Obsolete FPGA Technology to Achieve Design Continuity
Vladislav Palfy, Director Application EngineeringMany designs targeted to obsolete FPGAs are still functionally viable, but old FPGAs are no longer available to support the design or acquiring these obsolete FPGAs is cost prohibitive. The time, resources, and cost of redesigning onto newer FPGAs may not be practical. Re-synthesizing the RTL to meet the desired new technology may also not be feasible: there are many pitfalls associated with this process that can lead to errors finding their way into the design. Adding to the dilemma is the fact that new FPGA technology offers significant benefits that obsolete technology doesn’t have in terms of safety, security, trust, and power-saving features, while designs on obsolete technology can be inadequate to meet the stringent demands of today’s market. Retargeting these designs to newer FPGA technology extends the life of designs and ensures that designs are brought up to the latest safety and security standards while reducing power consumption. This presentation will introduce OneSpin’s FPGA Retargeting Solution, which can alleviate these challenges and effectively extend the lifespan of designs residing on old or obsolete FPGAs.
14:00 Introductory Overview: Certification Training for Formal Verification Methodologies
Vladislav Palfy, Director Application Engineering, OneSpin; and Christopher Diltz, Senior Verification Engineer, Edaptive ComputingThe design and implementation of integrated circuits has exploded in growth in recent years. ICs have found applications in diverse areas, such as transportation, security, and the Internet of Things (IoT). This growth has led to increasingly complex design implementations that require more thorough and exhaustive verification test runs. With smaller time-to-market requirements, verification engineers face a bottleneck in the time it takes to exhaustively verify and sign off on a design. As a result, verification engineers are looking to apply more exhaustive verification methodologies and identify tricky corner case bugs that other verification methodologies would miss. This overview session will highlight the announcement of a joint ECI-OneSpin Introductory Certification Training Course on Formal Verification Methodologies and their application to design use cases. We will offer an overview of the goals of the class, outline the structure and agenda, and explain the certification exam process and future classes.
14:15 Breakout Sessions
Select the small group discussion topic that most appeals to you. You’ll have the opportunity to ask questions, share your thoughts, and bounce ideas off of others who are facing similar design and verification challenges.
Topic One: The Ins and Outs of Trust and Assurance
Discussion Moderator: John Hallman, Product Manager Trust & Security, OneSpinThe modern world relies on complex electronic systems. Military and aerospace applications, defense systems, and other critical infrastructure must all be resilient to adversary attacks that could compromise the safety and privacy of the American people. In the past, security engineering has focused on software and system-level issues, but there is ample evidence that ever more risks and attacks involve hardware. Embedded systems using relatively simple processors are not exempt. Malicious actors may construct misuse-case scenarios, exploit hardware weaknesses, and/or insert Trojans. Hardware assurance (HwA) is critical to build secure systems from the ground up. Join this breakout session to share your thoughts on the rapidly evolving landscape of trust and assurance, discuss the DoD's needs in verification, and brainstorm ideas to solve complex problems on the horizon.
Topic Two: RISC-V and the Open Source Movement
Discussion Moderator: Sven Beyer, Chief Scientist, OneSpinThe RISC-V movement has opened up new frontiers of possibility and flexibility when it comes to processors. With great freedom comes great responsibility: to verify designs for ISA compliance, that is! RISC-V has the potential to be of significant benefit to military and aerospace designers, but exhaustive verification and proof of instruction set architecture compliance are essential. Join this breakout session to explore the far-reaching effects that RISC-V and the broader open source movement have had on electronics and to engage with others who are using RISC-V for a candid discussion of the best practices for incorporating open-source hardware into your designs.
Topic Three: Safety and Standards in Mil/Aero: What's Next for Hardware Safety Compliance?
Discussion Moderators: Jörg Grosse, Product Manager Functional Safety, OneSpin; and David Landoll, Solutions Architect and North American DO-254 Users' Group Member, OneSpinFunctional safety standards ISO 26262 for automotive and DO-254 for avionics are different, but they address similar concerns and share certain high-level requirements. Are organizations and products that are compliant with ISO 26262 well-positioned to address DO-254? As the DoD strives for dramatically shorter product development cycles, could ISO 26262 automation techniques and best practices be leveraged in mil/aero projects? Join this session to share your opinions and experiences with DoD safety compliance challenges.
14:45 Breakout Session Summaries
Moderator from each breakout session will offer highlights and key takeaways from the discussion.
14:55 Closing Remarks
OneSpin Master of Ceremonies
Meet Our Speakers
Get to know our keynote speakers, users, and experts
Speakers are listed in order of appearance on the program
Len Orlando | Air Force Research Laboratory
Air Force Hardware Assurance Lead, Office of the Secretary of Defense, Trusted and Assured Microelectronics (T&AM) Program
Len Orlando graduated from the Ohio State University in 2001 with a Bachelor of Science in Electrical and Computer Engineering. After receiving his degree, Mr. Orlando joined the Air Force Research Laboratory Sensors Directorate, developing next generation digital receiver exciter technologies in advanced SiGe bipolar, CMOS, and III‐V foundry offerings.
In 2008, Mr. Orlando received his Master’s Degree in Electrical Engineering from the University of Dayton with his thesis entitled, “Digitally Controllable Variable Gain and Variable Slope High Performance X‐Band Amplifier.” Over the course of his AFRL career, Mr. Orlando has provided subject matter expertise, participating as part of a select government team on DARPA TEAM, NeoCad, HEALICs, COSMOS, TRUST and IRIS programs.
Today, Mr. Orlando is the AF Hardware Assurance lead for the Office of the Secretary of Defense (OSD) Trust and Assured Microelectronics (T&AM) Program contributing to the DoD’s renewed interest in state-of-the-art microelectronics for national security.
Mr. Orlando will welcome attendees to the first day of Osmosis for DoD with opening remarks for the Department of Defense and Trusted Silicon Stratus communities.
Matthew Casto | Office of the Secretary of Defense
Director, Trusted and Assured Microelectronics (T&AM) Program
Dr. Matthew Casto serves as Director for the Trusted and Assured Microelectronics (T&AM) Program within the Office of the Secretary of Defense for Research and Engineering. Dr. Casto manages the DoD's T&AM and Microelectronic Innovation for National Security and Economic Competitiveness (MINSEC) Initiative, developing a new trust and assurance approach and delivering microelectronics innovation to realize the top modernization priority of the DoD.
Dr. Casto provides leadership, vision, and direction in the development of Future Years Defense Program (FYDP) execution, including planning, programming, and budgeting of resources, facilities, and personnel across all DoD services, agencies, and the intelligence community. Dr. Casto has held various government technical leadership positions in his 18+ years of civil service, including Special Assistant to the AFRL Commander and Chief Scientist, Chief of the Air Force Research Lab Sensors Directorate Trusted Electronics Branch, and as the Air Force's Principle Engineer and Hardware Assurance technical lead for the DoD Joint Federated Assurance Center. Matt holds BS and MS degrees from Wright State University and a PhD in Electrical Engineering from The Ohio State University. He is a member of the IEEE and has authored 40+ publications, patents, and invited talks on microelectronics, semiconductors, and advanced electronics technology.
Dr. Casto will open the first day of Osmosis for DoD with a keynote address to the Department of Defense and Trusted Silicon Stratus communities.
Ratish Punnoose | Sandia National Laboratories
Distinguished Member of Technical Staff
Dr. Ratish Punnoose is a Distinguished Member of Technical Staff at Sandia National Laboratories in Livermore, California. He provides technical leadership on the design and development of embedded systems for weapon components and has helped to incorporate formal verification as part of Sandia's digital design process.
Ratish leads much of the formal verification of ASIC-based designs at Sandia. He is part of a group of Sandia researchers developing formal tools to specify system behavior and to create certifiably correct systems for high-consequence applications. Ratish has a PhD in Electrical and Computer Engineering from Carnegie Mellon University.
At Osmosis for DoD, Ratish will present a case study entitled Ensuring Completeness of Formal Verification with GapFree: To End or Not to End (Property Writing).
Garrett Chan | The Aerospace Corporation
Garrett Chan is the Section Manager for the Hardware Security & Specialty Engineering section within Cyber Defense Solutions Department at the Aerospace Corporation. In this role, he leads the development of prototypes and providing customer support in areas relating to: embedded and trusted computing, integrated circuit vulnerability analysis, supply chain risk management, hardware Trojans, and more.
Prior to joining Aerospace, Garrett worked as an ASIC/FPGA Verification Engineer at NASA JPL, supporting missions such as Europa Clipper. Garrett also has previous experience from time spent as a Senior Electrical Engineer at Raytheon, as well as ASIC Design and Verification Engineering work at Emulex. Garrett holds both a MS and BS in Computer Engineering from California State University Long Beach.
At Osmosis for DoD, Garrett will present a case study entitled Evaluation of OneSpin Trust Assessment Platform for Hardware Trojan Detection.
Vikram Rao | The Aerospace Corporation
Senior Engineering Specialist
Vikram Rao joined the Aerospace Corporation in 2002, after graduating with an MS in Electrical Engineering from the University of Illinois at Urbana-Champaign. Rao spent 11 years in the Digital and Integrated Circuit Electronics Department, where he performed FPGA and ASIC quality audits and risk assessments, and FPGA prototyping for proof-of-concept in support of several national security space programs.
Since joining Aerospace’s Cybersecurity Subdivision in 2014, Rao founded the Hardware Security and Specialty Engineering (HSSE) section to address the growing hardware assurance gap in the mil/aero industry. He led a team focused on hardware security guidance, vulnerability and risk assessments, and independent hardware security research, with special emphasis on hardware Trojans. In his new role as project lead, Rao and the HSSE section are supporting ASIC/FPGA assurance efforts across multiple national security space and terrestrial programs.
At Osmosis for DoD, Vikram will present a case study entitled Evaluation of OneSpin Trust Assessment Platform for Hardware Trojan Detection.
Nick Darby | Battelle Memorial Institute
Nick Darby, a graduate of The Ohio State University and Miami University, has been a data scientist at Battelle Memorial Institute since 2017. He is the primary technical integrator for Battelle’s contributions to Trusted Silicon Stratus for Air Force Research Laboratory (AFRL). He also serves as the AI/ML lead for Battelle’s Rapid Assembly Inspection for COTS Security (RAICS) tool.
Nick is involved in the microelectronics assurance community as a member of the SecureAmerica roadmap working group, and the TAME Forum’s Hardware Assurance and Weakness Collaboration and Sharing (HAWCS) working group.
At Osmosis for DoD, Nick will present a case study entitled Leveraging OneSpin for Automated Risk Assessment.
Christopher Diltz | Edaptive Computing Inc.
Senior Verification Engineer
Dr. Christopher Diltz is a senior verification engineer at Edaptive Computing Inc (ECI), specializing in formal verification methodologies. He has three years’ experience of applying a broad suite of formal verification capabilities to address problems for both block level and system level verification. His skill set includes verification capabilities, such as scoreboard checking, equivalence checking, and RISC-V verification.
Chris also leads the hardware verification training program at Edaptive Computing. The hardware verification training program is part of ECI’s efforts towards workforce development to train a professional workforce for assured and secure microelectronics.
At Osmosis for DoD, Chris will present a case study entitled TSS SoC Sign-Off Methodology and an introductory overview of Certification Training for Formal Verification Methodologies in collaboration with OneSpin.
Paul McHale | Edaptive Computing Inc.
Principal Verification Engineer
Paul McHale is a principal verification engineer at Edaptive Computing Inc (ECI). He has over 25 years of experience as an electrical engineer spread across a unique set of roles. As the ever-changing industry gave birth to giants like Microsoft, the subsequent market reshaping created orthogonal opportunities preventing conflict with current or previous employment.
Embracing the diversity of opportunity resulted in a pleasant range of experiences from small, high-velocity startup like environments to large international corporations. From career-track centric employment to working at his own consulting company to working for a rep firm consulting group, most valuable to Paul is the very unique group of talented people he has been fortunate enough to work with on this exciting journey.
At Osmosis for DoD, Paul will present a joint case study with Air Force Research Laboratory (AFRL) entitled Securing RISC-V Military Projects.
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