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57th Design Automation Conference

Virtual Event | July 20–24, 2020

Find OneSpin on the Virtual DAC Conference Program

DAC is going virtual for the first time, and Team OneSpin will be there!

OneSpin’s experts and partners will share their expertise and insight in the following sessions:

Automated Trustworthiness Assessment of Third-Party Semiconductor IPs

John Hallman, Product Manager Trust & Security | Poster: Tuesday, July 21, 7:30–8:30 AM PDT | Paper: Thursday, July 23, 1:30–3:00 PM PDT

Developers of safety- and security-critical SoCs can no longer afford to ignore the risks of security vulnerabilities when integrating third-party IPs. Re-verification of an IP is not feasible, and the cost is prohibitive, even more so when the implementation-level expertise is not in-house. Verification and code reviews are likely to miss stealthy Trojans or vulnerabilities that surface in deep corner-case, misuse scenarios that are far from the IP intended usage. Some solutions are emerging to address these challenges. The Aerospace Corporation and OneSpin will share results of the application of an automated IP trust and assurance flow on over 90 RTL designs.

Learn more with John Hallman at the Trends in Meeting IP Challenges for a New Decade session (19.2) on Thursday, July 23 at 1:30 PM PDT. You can also catch him during the Design, Embedded, and IP Track Poster Live Q&A on Tuesday, July 21 at 7:30 AM PDT.

Security and Trust Assurance of RISC-V Open-Source Cores RocketCore and OpenHW CV32E

Sven Beyer, Product Manager Design Verification | Poster: Tuesday, July 21, 7:30–8:30 AM PDT

RISC-V has reinvigorated the open-source hardware community. Many individuals, companies, and organizations, including the OpenHW Group, are continuously releasing new and updated implementations of the RISC-V ISA. However, thorough functional verification of processors is very costly. Established IP providers using proprietary architectures have decades of experience and enormous resources dedicated to functional verification. And yet, security issues are routinely missed. RISC-V makes it possible and affordable to take the assurance and security verification of processor cores to the next level, matching or even exceeding the quality of established IP providers.

Edaptive Computing and OneSpin will share results of the application of a RISC-V formal verification solution to two cores (RocketCore and OpenHW CV32E40P). Learn more with Sven Beyer at the Designer, Embedded, and IP Track Poster Session (126.53) on Tuesday, July 21 from 7:30 to 8:30 AM PDT. 

Analysis of Faults in Safety Mechanisms and Computation of ISO 26262 Metrics

Jörg Grosse, Product Manager Functional Safety | Poster: Tuesday, July 21, 7:30–8:30 AM PDT

Quantitative FMEDA for automotive applications and compliance with ISO 26262 can be challenging. Fault injection can be used for deriving hardware safety metrics. However, for complex chips or semiconductor IPs with a variety of safety mechanisms, using fault simulation is laborious and time-consuming. What are the right stimuli to use? How can I speed up fault simulation? How can I detect early in the flow if the safety architecture will not get me to the target SPFM and LFM metrics, whether my goal is an ASIL-B, ASIL-C, or ASIL-D system? The good news is that there are alternative ways to approach the problem that can reduce or even eliminate the need for fault simulation.

Learn more about how to implement a streamlined, automated, and efficient quantitative FMEDA flow with Jörg Grosse at the Designer, Embedded, and IP Track Poster Session (126.34) Live Q&A on Tuesday, July 21 from 7:30 to 8:30 AM PDT. 

The Role of Equivalence Checking for FPGAs in Nuclear Applications

Jürgen Dennerlein, Platform Architect & Hardware Developer, Framatome | Poster: Tuesday, July 21, 7:30–8:30 AM PDT

The IEC SC 45A standard series regulates electronic instrumentation and control equipment in nuclear applications. In particular, IEC 62566 focuses on FPGA development activities, including verification of the post-synthesis and post-place-and-route netlists. How can you reduce the need for slow gate-level simulations? How can you be sure that the implementation tools have not introduced errors? Is that possible when using more advanced implementation flows? Luckily, there are formal verification tools that are dedicated to FPGA flows. Within a few days of effort, it is possible to exhaustive verify large netlists. Crucially, these tools are independent of the implementation tools, an essential requirement from safety standards.

Learn more with Jürgen Dennerlein from Framatome at the Designer, Embedded, and IP Track Poster Session (126.83) Live Q&A on Tuesday, July 21 from 7:30 to 8:30 AM PDT. 

Formal Verification of RISC-V Cores

Salaheddin Hetalani, Field Application Engineer | RISC-V Pavilion Presentation: Tuesday, July 21, 11:30 AM–12:00 PM PDT

OneSpin is a proud member of RISC-V International and the OpenHW Group. As part of our participation in the Virtual DAC RISC-V Pavilion, FAE Salaheddin Hetalani will give an overview of how formal verification offers critical advantages when it comes to ensuring that designs incorporating open source hardware are free of bugs and other issues. Featured in the presentation are a number of case studies involving successful verifications with OneSpin's RISC-V Verification App, which automates and accelerates verification to ensure proof of compliance to the RISC-V instruction set architacture (ISA) with no gaps or inconsistencies.

Join Salaheddin Hetalani on Tuesday, July 21 from 11:30 AM to 12:00 PM PDT to watch his presentation and participate in a live Q&A session. 

A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-of-Order Processors

Mohammad Rahmani Fadiheh, Technische Univ. Kaiserslautern | Paper: Friday, July 24, 2:00–3:00 PM PDT

Since the discovery of the Meltdown and Spectre in early 2018, micro-architectural side-channels and transient execution attacks have become a gold mine for security researches and, possibly, hackers. While there are no systematic processes and tools that address this risk comprehensively, research efforts are showing promising results. “A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-Of-Order Processors,” is authored by staff at the University of Kaiserslautern, Germany; Stanford University, California; and OneSpin President and CEO Raik Brinkmann. The paper extends their previous work on Unique Program Execution Checking (UPEC), which is based on formal methods, and demonstrates that it is possible to analyze a processor RTL implementation and systematically detect vulnerabilities that can derive from the processor microarchitecture and even from minor implementation choices.

Learn more at the Trust ... but Securely Verify! research session (87.3) on Friday, July 24 from 2:00–3:00 PM PDT.

Accellera’s Functional Safety Working Group Addresses Standardization Efforts to Improve Automation, Interoperability, and Traceability

Alessandra Nardi, Functional Safety Working Group Chair, Accellera Systems Initiative | Thursday, July 23, 2020, 12:00–1:00 PM PDT

Accellera Systems Initiative, the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, recently formed the Functional Safety Working Group (FSWG). Its mission is to develop a standard to provide a comprehensive and unified definition of the Functional Safety intent to improve automation, interoperability, and traceability across the Functional Safety development lifecycle of electronic circuits and systems.

Safety and Security Consultant Mark Hampton represents OneSpin on the FSWG. 

Join Accellera for your virtual lunch break as they present an overview of the scope, needs, and goals defined by the FSWG including developments since its formation. The session takes place on Thursday, July 23, 2020 from 12:00–1:00 PM PDT. There will be a live Q&A session to follow the panel discussion.


Visit Our Virtual Exhibit

Talk to our experts about the latest in IC integrity, including:

Functional Correctness Solutions

  • Verification Planning Integration and Verification Coverage IntegrationTwo Great Apps that Go Great Together to Minimize Overlap Between Formal and Simulation 
  • Operational Assertions – Turbocharge Your Assertions for More Expressive Power and Better Formal Performance
  • Connectivity XLKicking Formal Connectivity Checking Up to the Multi-Billion Gate Notch 
  • Floating-Point Unit VerificationAre Your Machine Learning and Deep Learning Chips Up to Snuff?
  • Equivalence Checking for Big Data, High-Bandwidth ApplicationsWhen High Optimization and Quality of Results Matter
  • Trying to Understand Your Coverage Making You Cross-Eyed? Get a Clear Picture with OneSpin PortableCoverage
  • Take the Risk Out of Implementing RISC-V – Complete Verification Is Quickly Achievable

Safety Verification Solutions

  • Fault Contribution AnalysisSafety-Aware SoC Partitioning for Automated, ISO 26262-Compliant FMEDA 
  • Fault Detection AnalysisAccurate Diagnostic Coverage with no Testbench or Fault Simulation Required
  • Don’t Get Lost on the Road to Hardware SafetyLet OneSpin ISO 26262 Safety Solutions Guide Your Way

Trust and Security Solutions

  • RISC-V Trust AssuranceThe Bad Stuff Can’t Hide

 

Want to learn more?

This is just the latest in our suite of verification offerings. Our experts are keen to learn more about the design and verification challenges that your team is facing. Let's schedule a call or a face-to-face meeting to explore your upcoming design projects and brainstorm about how we can work together to achieve your verification goals.