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On February 28, 2013, Ed Sperling, Editor-in-Chief of System-Level Design sat down to discuss verification strategies and changes with Harry Foster, chief verification scientist at Mentor Graphics: Janick Bergeron, verification fellow at Synopsys; Pranav Ashar, CTO at Real Intent; Tom Anderson, vice president of marketing at Breker Verification Systems; and Raik Brinkmann, president and CEO of OneSpin Solutions. Part 2 of the discussion is presented by System-Level Design Community.
Turns out at the EDAC CEO Panel, Rich Valera of Needham & Company presented a survey of EDAC members that cited Oasys, OneSpin, and Berkeley as EDA's top 3 "hottest" start-ups.
System-Level Design sat down to discuss verification strategies and changes with Harry Foster, chief verification scientist at Mentor Graphics: Janick Bergeron, verification fellow at Synopsys; Pranav Ashar, CTO at Real Intent; Tom Anderson, vice president of marketing at Breker Verification Systems; and Raik Brinkmann, president and CEO of OneSpin Solutions. What follows are excerpts of that discussion.
Formal verification can be used for many things, but one is to ensure that synthesis performs correctly and that the behavior of the output netlist is the same as the behavior of the input RTL. OneSpin EC equivalence checking ensures that the RTL design and the output gate-level netlist will produce the same results for the same inputs under all circumstances.
OneSpin Solutions and Oasys Design Systems have signed an original equipment manufacturer (OEM) agreement. OneSpin 360 EC-ASIC is being used for synthesis verification, comparing two representations of the same design before and after synthesis to ensure functional equivalence.
A few weeks ago, I asked many people in the industry for their predictions for 2013. I separately asked for those related to technology in general, to the EDA industry and for business predictions. In this first part I will be presenting their technology predictions.
