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ATopTech, ClioSoft and OneSpin Solutions are sponsoring free three-day exhibit floor passes to the 2016 Design Automation Conference (DAC). For the eighth year, the “I LOVE DAC” badge provides access to keynotes, the DAC Pavilion and the exhibition floor which includes over 180 exhibitors, the new World of IoT exhibit, a food court featuring local favorite selections and more. DAC is the premier conference devoted to the design and automation of electronic systems. The conference offers outstanding training, education, exhibits and networking opportunities for designers, researchers, tool developers and vendors. The 53rd DAC will be held at the Austin Convention Center in Austin, Texas, from June 5 - 9, 2016.
John Cooley's popular DeepChip website published a comprehensive 5 part guide to Formal Verification. This is a must read for anyone considering using the technology on their own projects, or even for those simply interested in the latest in verification technology.
The use of formal verification technology as a mainstream technique for system-on-chip (SoC) designs is, at last, becoming a recognized approach to combat the verification gap. A recent survey suggests that formal assertion-based verification (ABV) is now used on 26 percent of chip design projects. However, the promise of this alternative approach to classic simulation has taken many years to bear fruit, and still only advanced verification environments incorporate it. Why is this and what can we learn from its use so far to make it available to the SoC engineering community at large?
Another area that has seen growing acceptance in the past few years is Formal Verification. “Formal continues to be deployed in situations where preset applications work well,” says Kelf. “More advanced applications such as system security analysis and system-level verification testing will emerge.”
Kelf also predicts that the most important development for formal in 2015 will be “a proliferation of the technology to designers where it may be used to speed up the early checking of design code before it is submitted into the verification regression environment.”
