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In the news

Verification Unification | Experts at the Table, Part 2

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By Brian Bailey, Semiconductor Engineering

Darbari: You are getting your assumption, you are getting constraints, and you are getting coverage points and you are getting your checkers. These three aspects and the ability to exercise them in formal or run them in a testbench environment on an emulator target or even in an FPGA are great. When we talk about formal’s usage we say it could be done from the block level to the IP level, to the system level or you could leave them running in an emulation target. I have to ask where is the formal?

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Formal verification assumes starring role in automotive

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David Kelf on Embedded Computing Design

June is National Safety Month and a great time to look at the tremendous advances in automotive technology, much of it related to ensuring the safety of the car’s driver and passengers. Anyone buying a smart vehicle today will get options to assist them with parking, lane management, and braking.

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Safety Plus Security: A New Challenge

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By Brian Bailey, Semiconductor Engineering

The challenge is knowing which parts of the hardware to concentrate on. “This could include redundant register files, added ECC protection in memory, redundant CPU core so that you can go lock-step,” says Ashish Darbari, director of product management for OneSpin Solutions. “While you may add a lock-step CPU, you may not need to duplicate all of the register files. There is a lot of design architecture knowledge that is applied. The challenge is measuring if it does the job.”

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DAC 2017 preview: OneSpin

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By TDF Editor, TechDesign Forum

Verification specialist OneSpin has posted the landing page for its activities at the 2017 Design Automation Conference (DAC 2017) in Austin, Texas, later this month (June 18-22). The company is participating in a range of events as well as exhibiting at Booth #1547 in the Austin Convention Center.

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The Week In Review: Design

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By Jesse Alen, Semiconductor Engineering

OneSpin revealed new formal applications focused on random fault verification for safety critical analysis in automotive and other mission-critical applications. The Fault Injection App provides controlled injection of faults and assertion mapping to associated fault scenarios, as well as visibility into corrupted design behavior.

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Verification Cowboys

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By Brian Bailey, Semiconductor Engineering

Brinkmann suggests that startups may have an advantage over the more established players. “Startups today are very different from 10 years ago. It is no longer easy to find your key customer and grow it into a revenue stream. The technology is getting more difficult and you need more time to get a viable product out. There are several other challenges.

One is the acceleration of the innovation speed. Our customers need to innovate at a higher pace, and they need new capabilities. But it is not always easy to find the right solution for the problem. That is also an opportunity for small startups because we can look into the problems deeper and quicker and provide solutions. That enables us to leverage a community of smaller companies.”

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Verification Unification | Experts at the Table, Part 1

By Brian Bailey, Semiconductor Engineering

The verification task relies on both dynamic execution and formal methods today, but those technologies have few connection points. That may be changing with Portable Stimulus.

There is a lot of excitement about the emerging Accellera Portable Stimulus Working Group (PS) standard. Most of the conversation has been about its role in simulation and emulation contexts, and in the need to bring portability and composability into the verification flow. Those alone are strong enough reasons to see strong adoption, but it appears that Portable Stimulus and formal verification have several interesting possibilities together. This could strengthen both technologies and eliminate some of the overlap between them.

Semiconductor Engineering brought together industry luminaries to initiate the discussion about the role that formal technologies will play with Portable Stimulus and how it may help to bring the two execution technologies closer together. Participating in this roundtable are Joe Hupcey, verification product technologist for Mentor, a Siemens Business; Tom Fitzpatrick, verification evangelist for Mentor and vice chair of the Portable Stimulus Working Group (PSWG); Adnan Hamid, chief executive officer of Breker Verification Systems; Roger Sabbagh, vice president of applications engineering at Oski Technology; Sean Safarpour , director of CAE for VC formal at Synopsys; Tom Anderson, who was product manager at Cadence at the time and secretary of the Portable Stimulus working group; and Ashish Darbari, director of product management for OneSpin Solutions. What follows are excerpts from that conversation.

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