RISC-V Verification Challenges Spread
By: Ann Steffora Mutschler
Continuous design innovation adds to verification complexity, and pushes more companies to actually do it.
“It is relatively easy to add a few custom instructions on top of an existing processor,” said Sven Beyer, product manager at OneSpin Solutions. “Performance and code size analysis are not easy, but in many cases one can isolate the effects of these changes and make sure they provide the desired results for the target workloads. Functional correctness and security assurance, on the other hand, may have to be reconsidered from scratch for the entire core. The big challenge is to automate not only the generation of the core tool chain for the optimized processor, but also the verification. The key here is to go beyond compliance and exhaustively verify with a largely automated flow that the micro-architecture implements the desired instruction set architecture with its custom instructions without any additional functionality or unintended side-effects.”
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“There’s a design ecosystem around the IP, there’s a software ecosystem around the OSes, but there’s also a verification ecosystem,” Davidmann said. “We’re working very hard to evolve. RISC-V International has a key part to play, and there are two things it needs focus on. One is the specifications to ensure they’re tight and clear, and to ensure that everybody is understanding the same thing. The other is compatibility and architectural compliance that they’re going to do because it’s essential that we don’t get fragmentation out there; that we can make use of the tools, make use of the compilers, make use of the software. The ecosystem could do a lot, and RISC-V International, and the members can do a lot to help the vibrance of RISC-V, and to help it evolve successfully.”
