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RISC-V Becoming Less Risky With The Right Verification

By: Rob van Blommestein

Detecting critical bugs in an open-source core for high-volume chips with formal verification.

Arjan Bink, principal architect at Silicon Labs and chair of the OpenHW Cores Task Group, went on to say: “The pinpointing of the issues’ root cause was impressive and a massive time-saver in debug. The solution also showed almost zero noise in detecting real RTL bugs, as opposed to other approaches where the issues reported often lead to fixes in the verification environment.”

Check out the OpenHW TV episode titled “Deep Dive into Formal Verification for the CORE-V CVE4” featuring our very own Sven Beyer, RISC-V product manager, to learn more about how OneSpin contributed to the verification effort.


The OpenHW CV32E40P core is fully verified and ready for use, but there are still some verification challenges that designers will need to overcome when integrating the core: especially in cases where the core is customized. This core, and other RISC-V cores like it, should be re-verified after integration or customization to ensure that any changes do not introduce new bugs or produce unwanted behavior—and formal verification is the way to eliminate risk and exhaustively prove that everything is as it should be.


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