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Over-Design, Under-Design Impacts Verification

By Ann Steffora Mutschler, Semiconductor Engineering

How and when a design is verified can mean the difference between success and failure.

Designing a complex chip today and getting it out the door on schedule and within budget — while including all of the necessary and anticipated features and standards — is forcing engineering teams to make more tradeoffs than in the past, and those tradeoffs now are occurring throughout the flow.

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Ultimately the verification environment should serve the design under verification, but in many occasions, ‘reuse’ comes in, observed Sergio Marchese, technical marketing manager at OneSpin Solutions.

“One may try to re-use an existing verification infrastructure that may not be a good fit, perhaps to please a manager that need to show the effort savings delivered from previous investments,” Marchese said. “But a few late bugs, or even just a missed one, can quickly overcome these savings. On the other side of the spectrum, the temptation to justify the additional effort of over-design with the claim that building a more flexible, reusable verification environment will eventually pay off, is also risky.”

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