Formally Verifying SystemC/C++ Designs
By Rob van Blommestein
As the level of abstraction increases, so too must the level of verification.
We’re seeing an increase in the number of designs employing SystemC/C++. This isn’t surprising given the fact that specific use models have emerged to drive common design flows across engineering teams leading to the adoption of high-level synthesis (HLS) at many large semiconductor and electronic systems companies. These HLS tools are a popular method to rapidly generate design components with varying microarchitectures, while optimizing algorithm processing datapaths rapidly and effectively.
