Formal Verification Of Floating-Point Hardware With Assertion-Based VIP
By: OneSpin Solutions
An alternative floating-point hardware verification approach based on a reusable, IEEE 754 compliant SystemVerilog arithmetic library.
However, solutions often rely on a mix of the following: hard-to-use formal tools; highly specialized engineering skills; availability of a suitable executable model of the hardware; and significant, design-specific engineering effort. In this paper, we present an alternative floating-point hardware verification approach based on a reusable, IEEE 754 compliant SystemVerilog arithmetic library. While not addressing all verification challenges, this method enables engineers to set up a formal testbench and uncover deep corner-case bugs with minimal effort. Results from industrial applications are reported.
