Debugging Embedded Applications
By Ann Steffora Mutschler, Semiconductor Engineering
Software and hardware interdependencies complicate debug in embedded designs. New approaches are maturing to help reduce debug time.
Debugging embedded designs is becoming increasingly difficult as the number of observed and possible interactions between hardware and software continue to grow, and as more features are crammed into chips, packages, and systems. But there also appear to be some advances on this front, involving a mix of techniques, including hardware trace, scan chain-based debug, along with better simulation models.
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“Formal verification provides faster runtime than simulation, allowing simulation licenses to be freed up for other tasks like integration testing,” noted Rob van Blommestein, head of marketing for OneSpin, a Siemens Business. “Set up is also much quicker and easier. RISC-V’s flexibility to create custom instructions creates a verification hurdle for simulation. Formal technology easily can be applied to verify custom extensions and instructions. Complete coverage of all corner cases can be achieved with formal with minimal to no effort in the development of the testbench. Unspecified behavior, such as undocumented instructions, also can be uncovered using formal. The engineering team will be able to understand coverage progress as it relates to ISA requirements throughout the verification process. Direct traceability of verification and coverage can be achieved.”
