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Addressing safety critical FPGA designs

By: Rob van Blommestein

Advanced EDA tools and methodology are helping designers to avoid synthesis bugs in safety-critical FPGA designs.

Field-programmable gate arrays (FPGAs) are the dominant hardware platform in many safety-critical, low-volume applications, including aerospace and nuclear power plants (NPPs). Modern FPGA devices feature integrated microprocessor cores, digital signal processing (DSP) units, memory blocks and other specialised intellectual properties (IPs) and these advanced devices allow for the implementation of large, high-performance system-on-chip (SoC) designs with integrated safety mechanisms, making a strong case for adoption in additional safetycritical applications traditionally dominated by application-specic integrated circuits (ASICs).


FPGAs have long been the hardware platform of choice in many low-volume safety-critical applications. Nowadays, these devices can implement complex functions while fullling tough performance and power goals, competing with ASICs also on high-volume safety-critical applications, including automotive. The availability of advanced EDA tools and methodology is crucial to support this trend. ASIC development has used formal EC for nearly 20 years. Automated formal checks prior to synthesis are also widely adopted by ASIC teams. The same technology is now available in FPGA development, enabling a robust, efcient implementation process. OneSpin’s formal signoff ow of FPGA implementation has been designed to be orders of magnitude more rigorous and efcient than GLS and lab tests. The technology is mature and proven on hundreds of industrial designs for communications, NPPs, and other safety-critical applications.



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