Design Automation Conference
December 5-9, 2021| San Francisco, CA
Join OneSpin: A Siemens Business in booth #1539
DAC Pavilion Panel: Handling SoC Verification: Changing the Paradigm in Verification Approaches
Time: Tuesday, December 7th 3:00pm - 3:45pm PST
Moderator: Brian Bailey - Semiconductor Engineering
Panelists:
Balachandran Rajendran - Dell EMC
Mike Chin - Intel Corporation
Adnan Hamid - Breker Verification Systems
Neil Hand - Siemens EDA
Description: Modern SoC complexity is driving a new verification frontier. The verification of an SoC has always been a departure from the more standardized techniques employed in large block or sub-system, both in terms of test requirements as well as sheer complexity and size. However, new issues such as safety, security, processor instruction flexibility layered on top of advanced applications including 5G, AI, Quantum Computing, etc. have driven the need for different thinking.
Simulators, emulators and formal-based apps are essential tools in the verification teams’ armament. But what is the most effective way to augment the core capabilities to deliver these intensely complex chips on time? For example, do we invest in accelerating test content production through techniques such as Portable Stimulus. Or should the focus be on additional and advanced static verification methods.
Moderator Brian Bailey, technology editor/EDA for Semiconductor Engineering, will lead two well-known, senior engineers who are responsible for next generation verification flow development. They will consider and discuss next generation needs and the directions they can take. Two vendor CEOs will attempt to address those needs and explain why their method is the most effective use of time and budget.
Come and witness an animated and lively discussion as we watch an open and frank conversation, often held behind closed doors in many semiconductor and electronic systems companies.
Designer Track Presentation:
Ensuring Completeness of Formal Verification with GapFree: Are we done yet? - Ratish Punnoose, Sandia National Labs - Tuesday, December 7th - 11:22am PST
Description: A challenge with formal verification of RTL designs is knowing how much verification is enough. This is especially true when it comes to knowing when to stop writing additional properties. How can we achieve confidence that enough properties have been checked to verify the correctness of the design? OneSpin's GapFreeVerification methodology provides an answer to this problem. The methodology results in an automated check of the written properties to ensure that all design behaviors have been captured. In this presentation, we’ll show you how we have applied the GapFreeVerification workflow to ensure completeness of verification.
Designer Track Poster Sessions:
Beyond Lint - Cedric Walravens, ICSense - Monday, December 6th 5:00pm - 6:00pm PST
Description: Managers often see verification as a necessary evil that consumes an outlandish portion of the overall project effort. Any means to reduce the verification effort, therefore, should be grasped with both hands.
Formal consistency checks are one such means. In addition to reducing effort, they can come extremely cheap in terms of engineering hours required. Key here is to provide a framework that enables designers to quickly check their designs before moving to simulation. In addition, a mechanism to create waivers that are not prone to code changes is necessary. Lastly, results must be reported concisely so that any unexpected changes are immediately spotted.
We present a working concept and novel TCL scripting that can be adopted in any Formal tool with TCL support.
Formal Verification of Safety Mechanisms - Keerthikumara Devarajegowda - Infineon Technologies AG Technische Universität Kaiserslautern - Tuesday, December 7th 5:00pm - 6:00pm PST
Description: This talk will highlight how formal verification is deployed to exhaustively verify designs that implement safety mechanisms such as Error Correction Codes (ECCs). ECC designs that encode a large data vector and detect multiple bit errors have been traditionally verified with simulation-based methods even though they are better suited for formal verification. The main reason was the scalability of formal verification for large ECC designs. Properties that are written to verify large ECC designs time-out without an outcome owing to limited memory or time resources. We discovered that a succinct characteristic of ECC designs can be exploited to achieve an exhaustive proof on large ECC designs. For instance, the proof runtime of a 3 bit error detection/correction property requires less than 2 hours for passing on a 256 bit ECC design. Previously, the same property timed out after running for 6 days. We successfully applied this approach to multiple instances of ECC designs implemented across several safety-critical automotive SoCs. Results show that the proof runtime of the properties leveraging the proposed approach decreases at least by a factor of 50, and scales proportionally with the width of the data vector and detection and correction capability of the codes.
Designer/IP/Embedded Systems Track Session: Identifying Security Weaknesses in Electronic Designs using a Standardized Methodology
Time: Wednesday, December 8th, 1:30pm – 3:00pm PST
Location: IP Track Room 2008 (Exhibit Hall 2nd Floor)
In-Person Presenters:
Mike Borza, Synopsys
Jason Fung, Intel Corporation
John Hallman, OneSpin Solutions
Vishal Moondhra, Perforce
Anders Nordstrom, Tortuga Logic
Jeremy Bellay, Battelle
Jason Oberg, Tortuga Logic
